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|$( Eh . h @ @L$@ L$D$0 D PD$ d$ T$ L$0!L$ @ PD$ @ ;|$0r@[^_]Í @ @D$< D$0~ L$0 L$$f @ PD$0@[^_@ ]t& <T$8% ЉD$$v h h @ T$<P Lf D$, l$D$ D$g @h$ / D$t, \$l$D$ D$B @h$ / D$T$0, D$ @ D$] T$@h$. D$L$<, |$D$ L$D$B @h$ / D$D$ D$ @ D$] D$, @h$. D$D$, D$ D$ @h$. D$L$4D$(D$ d$ T$ !D$ D$ UD$ D$ D$] D$, @h$. D$ D$T$<, D$ D$g T$@h$ / D$HT$0, D$ @ D$ T$@h$. D$ L$}, T$D$h D$ D$B @h$ / D$D$, D$h D$ D$g @h$ / D$dD$(D$ D$] D$, @h$. D$t& UWVSÃ(@ T$
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@ P @ @ P1@ @ P1 @ P1$ T$ H @ P L$ @ P D$ @ P T$ @ P @ P1 iD$ @ |$ L$$ (` h V @ PiD$ @ |$ T$$ 0(` p @ PiD$ @ |$ T$$ 4(` t d @ PD$ x/V
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@ P- @ PiD$ @ T$$ @ @ P @ PiD$ @ T$$ @ @ P @ PiD$ @ T$$ @ @ P @ PD$ x/ iD$ @ T$$ @ @ PI @ PiD$ @ T$$ @ = @ P0 @ PiD$ @ T$$ @ @ P1 @ PiD$ @ T$$ @ } @ P/ @ PD$ x@Z iD$ @ T$$ @ w @ P9 @ PiD$ @ T$$ @
@ P; @ PiD$ @ T$$ @ @ P< @ PD$ x 4 % = t@ z fiD$ @ |$ T$$ (` ` @ P|$ @!` C @ P1|$ !` M @ P, [^_]t& = ==P 2= '= D$ x iD$ @ T$$ @ @ PS @ PiD$ @ T$$ @ ) @ PT @ P1iD$ @ T$$t$ , ƍv @L$( @ T$ PW @ P @t @ T$ PX @ PD$(uiD$ @ T$$ @t$ @ PY @ PiD$ @ T$$ @ @ P[ @ PiD$ @ T$$ @ @ P @ PiD$ @ T$$ @ @ P @ P& = 0=P %= i@ `(` | D$ P& iD$ @ T$$ @ C @ PA @ PiD$ @ T$$ @ 5 @ PE @ PiD$ @ T$$ @ ' @ PK @ PiD$ @ T$$ @ @ PR @ Pv iD$ @ T$$ @ @ PG @ Pv iD$ @ |$ T$$ (` l C @ PD$ x@WiD$ @ |$ T$$ P(` x @ P@ |$ @ )h 7 1iT$ @ L$$d |$ )h z @ P@ |$ @ #h D 1|$ #h U @ P>1ɺ6&D$ D$ $` 6&1ɉD$ D$ $` |$ )h D$ |$t$D$ , D$B @h$ / D$T$(L$ , D$X T$L$ D$t @h$@/ D$ND$ l$D$W D$t D$ , @h$@/ D$L$ , l$D$ L$ D$t @h$@/ D$L$ , l$D$[ L$ D$t @h$@/ D$CL$ , l$D$Y L$ D$t @h$@/ D$L$ , l$D$T L$ D$t @h$@/ D$L$ , l$D$S L$ D$t @h$@/ D$L$ , l$D$ L$ D$t @h$@/ D$D$D$ t$D$g D$ , @h$ / D$ L$ , |$t$L$ D$ @h$ / D$L$ , |$t$L$ D$ @h$ / D$L$ , l$D$ L$ D$t @h$@/ D$L$ , l$D$- L$ D$t @h$@/ D$kL$ , l$D$3 L$ D$t @h$@/ D$L$ , l$D$( L$ D$t @h$@/ D$gL$ , l$D$% L$ D$t @h$@/ D$L$ , l$D$ L$ D$t @h$@/ D$c, D$ D$ D$P @h$. D$*L$ , l$D$< L$ D$t @h$@/ D$D$ t$D$ D$ D$ , @h$ / D$L$ , t$|$L$ D$ @h$ / D$, t$D$ D$P @h$. D$J, t$D$ D$P @h$. D$, t$D$ D$P @h$. D$, D$ D$ $ D$P @h$. D$ T$ , t$D$ T$ D$ @h$ / D$yL$ , t$|$L$ D$ @h$ / D$fL$ , l$D$; L$ D$t @h$@/ D$L$ , l$D$9 L$ D$t @h$@/ D$O, D$ D$ D$P @h$. D$, D$ D$ @ D$P @h$. D$L$ , l$D$1 L$ D$t @h$@/ D$ L$ , l$D$0 L$ D$t @h$@/ D$L$ , l$D$ L$ D$t @h$@/ D$L$ , l$D$ L$ D$t @h$@/ D$/L$ , l$D$A L$ D$t @h$@/ D$L$ , l$D$E L$ D$t @h$@/ D$L$ , l$D$K L$ D$t @h$@/ D$L$ , l$D$R L$ D$t @h$@/ D$L$ , l$D$I L$ D$t @h$@/ D$L$ , l$D$/ L$ D$t @h$@/ D$I, D$ D$ D$] @h$. D$9, t$D$ D$P @h$. D$L$ , l$D$ L$ D$t @h$@/ D$&D$ t$|$D$ D$ , @h$ / D$L$ , t$|$L$ D$ @h$ / D$D$ t$|$D$ D$ , @h$ / D$tL$ , l$D$G L$ D$t @h$@/ D$ D$ L$l$D$B D$ , @hL$$ / D$L$mD$T$ , l$D$g T$ @hL$$ / D$ L$ , |$t$T$ D$ @h$ / D$@ T$ |$t$T$ q' 0ɉt$$ֺ \$ É|$(|$4l$,@ t x@# D uQPȁ @ t x@# D ueP\$ t$$|$(l$,0, L$T$t$ D$ @hT$L$ $. D$@ L$ T$g, T$|$t$ D$ @hT$$. D$@ T$[t& ,ɉt$$ֺ \$ É|$(@ t x@# D uMPȿ @ t x@# D@ uZЋ\$ t$$|$(,Ë, L$T$t$ D$ @hT$L$ $. D$@ L$ T$kD$, |$t$ D$ @hT$$. D$T$hv 0ɉt$$ֺ \$ É|$(|$4l$,@ t x@# D uQPȁ @ t x@# D ueP\$ t$$|$(l$,0, L$T$t$ D$ @hT$L$ $. D$@ L$ T$g, T$|$t$ D$ @hT$$. D$@ T$[t& UW VSi@ 0҉T$(L$$ @ t x@# D g P1iD$(@ T$$l$(< $u䋃@ L$(P
L$,` L$ D$,` D$ @ @D$ @L @ T$ P @ T$ P1iD$(@ T$$ t& @/ @ T$ P@ T$ Pu@ T$ P @ @D$ @ @ T$ P @ T$ P1iD$(@ T$$l$(A $ u䋃@ f1L$,@` L$ @ |$,P1` iD$(@ T$$J D$ L$ @ @D$ T$L$$@ @T$!Ճ @ E@D$ @ P@ PD$$D$ _@ @D$ @ P 0[^_]L$(, l$t$L$ D$t @h$@/ D$D$$L$(D$ D$D$, L$ @h$@/ D$#L$(D$, D$ D$ L$ @h$@/ D$ @D$(t$D$ D$t D$ , @h$@/ D$L$(D$, D$ D$ L$ @h$@/ D$ @oD$(t$D$ D$t D$ , @h$@/ D$5D$(t$|$D$ D$ , @h$. D$@ ] ,ɉt$$ֺ \$ É|$(@ t x@# D uMPȿ @ t x@# D@ uZЋ\$ t$$|$(,Ë, L$T$t$ D$ @hT$L$ $. D$@ L$ T$kD$, |$t$ D$ @hT$$. D$T$hv UWV SÃ0ҋ@ T$(L$,t x@# D@ iT$(@ 1D$, D$(
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ع F - 1ɺ ع F - 1ɺ ع F = C = h - 1ɺ3 dع S1ɺ [^Cv 1ɺ 2t& 1ɺ t& 1ɺ$ t& 1ɺZ ;t& 1ɺ t& 1ɺ t& 1ɺ 9t& ~ i t& 1ɺ& RCt& 1ɺ4 :t& 1ɺ% "t& 1ɺs
t& W`> VSË @ F Pt- g 1ɺ 1ɺ 1ɉغ F - & 1ɉغ hF - 1ɺ I 8 '1ɺ 1ɉغ F = = = = 1ɺ 1ɺ |1ɺ n ]1ɺ O >1ɺ 0 ? 1ɺ 1ɺ ? 1ɺ 1ɺ 1ɺ ~ 1ɺ i X1ɺ J 91ɺ + 1ɺ ~ P 1ɺ 1ɺ r1ɺ d عhSF _! = 1ɺ ( ~ 1ɺ F - wc x g V1ɺ Hع 7ع &1ɺ[ [^_t& ع F = t- wX1ɺ 1ɺ & 1ɺ 3t& 1ɺ j=t& ع O1ɺ Aqt& 1ɺ *mt& 1ɉغ ع ع ع ع ع 1ɉغ ع 1ɉغ ع 1ɺ qDt& Wf ?f1ɺ *Bt& V1SË @ h 1ɺ 1ɺ 1ɺ ع F - 1ɺ y h W1ɺ Ih 8 '1ɺ ع F - v*1[ ^f1ɺ
Lt& 1ɺ ع 1ɺ [^VS ߿ @ s b1ɺ T CC - !1ɺ 1ɺ 1ɺ 0 @P`p 1ɺ r [^_& G!fV @ S P w0XpuX;X tC ʁ X[^Í& PpuX;X t PX1 & ' UWVSÃ4 @ G@ KC D$$ Cu C;C - KCC, C
2 u>C;C p- 2 kPSsKu;S M- 4C P, ع D@ wG - ' @ Uع @ DG P, = @ ,G = - C S CuC;C z, Cع @ G = i( = = t @ @ @ j kC KP퉃 % C;C + PkSsC 퉋 u;S + C P% ,@ sCP S uC;C J+ P C P@ KC S ɉ uC;C * Cع @ 0G PJ* = $ @ T@ C S CuC;C q* CG P\ $ ع @ G = uع @ G - aع @ `عb @ ?ع @ >b @ ع @ @ _ @ kC S 퉃 uC;C Z) C P% sC S uC;C ) C $@ G KC
S ɉ uC;C (
C P( C S CuC;C x( C Pt ,@ ,@ P$ kC( S 퉃 uC;C ( ( CG = ~= = ,@ sC+ KP " C;C ' + PkSsC 퉋 u;S W' C 0@ " kC S 퉃 uC;C & CG P\w6$x & ,@ 0 P@ sC S uC;C z& C P@ KC S ɉ r C;C && PkSsC 퉋 6 ;S % PkSsC 퉋 u;S % CG P = = - H@ ؽH@ H@ H@ sF M؍V WV HV8 9V< *V@ VP VT? VX V` Vd Vl Vp Vt Vx V| W F F؍ a O = + P m [ I 7 p % W F F؍ F PD؍ P ( ) , ' 0 & 4 o8 ]< ' KH 9L 'P T X \ ` d F PD؍ { i Pt JF PD؍ .
F? M؍$ ع ( G P = P hT VX DW F F؍d F M؍p x | P% v ع dG _ = * 5 p # p o ] K$ 9ع ( 'G P = C S + Cu>C;C + kPSsKu;S g 4C h@ `h@ h@ yS1CT$
l N T$$t䋓 p@ L$ p K u C;C T$ CE P2 = T$ !t;عp@ E P = a p@ SL$( p CT$ Ku(K;K L$ T$
L$ уKT$( 8p@ & p@ SD$(p KCT$ u(K;K L$ T$
L$ уK} T$(|} Pn p@ @ع p@ zE = - ~ ǔp { CD$ CC;C T$ <KCCL$ T$ C uC;C j CG = = @ 9 |@ " |@ v ` KC@ S ɉ uC;C @ CG = = R = w @ 9 }@ " }@ D$( t& L$( D$$
t$( @ @ l$ kCK 퉓 uS;S
Sع
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$C V V ع VG P\ $ P@ P@ % @ y M @ c~ % @ MhSp@ D$(p T$ S C u(K;K L$ T$
L$ уKT$( } p@ v V V@ P VHx xVP iVX Z PX V\ AG = sSt$ QV 0lt& V 1Tt& V <t& V $t& V t& V t& t$,f= - D$ - ? ҉C u S;S L$
SG P1 =
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W4[^_]Í& Vhع> SG T$ S& V\ t& VH@ Tt& t$( @ ƀ@ D$ t& L$ S C? K`C;C : D$ -? lfD$ - ? ҉C S;S
t$
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? PkSs K;S t D$(|$(
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s 5 T@ T@ T@ T@ [ |t& ? && ǔp { CD$ C C;C % U T$ Rt& D$ ks-? JC 4 S;S
S& P K uC;C k CVT VX V\ V` tVd eVh VVl GD$(|$(
_fp@ T$(|[v T$ !t{ع G - l R ع ع x h@ r 6 h@ DG - 0h@ 2 l+ع @ d@ bflO C PI ,@ D C C 3@ = |@ 4T$ tp@ i@ = }@ ~ @ hع 4@ b 4@ A ع 'G @ |@ |@ |@ ,|@ ` C@ S CuC;C ? kPSsKK;S 4CG = 3@ 8 }@ >Uع @ 8 @ p@ $@ ,@ M 赾 ؍ 蝾 苾
y@ k Y G 5 # $ < @ ۽H ɽT 跽X 襽\ 蓽d 聽p ot ]| K 9 ' ؉$ & D$ - ? C@ }@ 讼P 藼T 腼X p@ +C A P0 VCKE0 h@ $ h@ ع c@ G (@ ع @ P@ 踻 @ ع@ @4@ 茻ع 8@ {ع <@ j@@ Y fUWVSË @ F = = - Ճ 1 t& ~ u*K@ I QP C N t t ~ u*K@ I QP C ~ P" B F = < = h 9 CJ K@ I QP C K@ I QPp C jK@ I QP C;t& K@ I QP C K@ I QP C }K@ I QP Qt& X9 o{u'K@ I QP ~ 9 {B( BH V {P , (H V {P h V {u+@ C@ P Q F P = = g = \ 1ɺ V{\ p [^_]Ív ` fu*K@ I QP C v K@ I QP C K@ I QP Ct& uUK@ I QP K @ I QP C v1ɺ {K @ I QP S k@ C@ P Q p [^_]Ív K@ I QP SP E@ C@ P Q S @ C@ P QK @ I QP S @ C@ P Q S c1 t& @ C@ P Qu v K@ I QP S @ C@ P Q S ^@ C@ P Q S !@ C@ P Q SH @ C@ PhQ t& 1
t& @ C@ P Qu S @ C@ P Q S @ C@ P QK @ I QP S s@ C@ P Q S 6@ C@ P! Q ع O t& ! / t& ع t& ް Ͱ 輰1ɺ 记 v 1ɺ 蒰71ɺ $v ' UWVSÃ @ F@ D$ ?~ $ 111f D$uu +$9Ge uǃ{u+ @ C@ P Q D$t낍v $ ~D$ D$ 11+$v$D$ D$ +$9vƉNj$D$ D$ D$@t +$9vƉNj$D$ D$ D$ m +$9G$D?S C C;C _ $ kPSK ;S 6 ` {PSKux;S 4kPSKuV;S {CSu6;C sPSKu;S P C[^_]fdt& #v v v .v Tv 9v v hv qJ ' SË {PH t0P( [Í& K@ I QP! S u@ C@ P Q S ^@ C@ P Q S !@ C@ P Q S @ C@ P Q S @ C@ P Q S j@ C@ P Q S -@ C@ P Q S @ C@ P Q S @ C@ P Q S v@ C@ P Q ( [Ív ' VSÃxt [^Ít& 1 K @ I QP uʋ S u@ C@ P߿QK @ I QP߿ S .@ C@ P! Q [^
SË {P H1ɉ 蚨ع 艨1ɺ {ع jع Yع Hع 7ع &ع [t& K@ I QP S( #@ C@ P Q t& W VSË @ F Pt= 1ɺ h ع WF _m = 1ɺ , ~ 1ɺ ަ1ɺ Ц 迦 讦 蕦1ɺ$ 臦 v e T C 2{X ( F = = = = = 1ɺ ȥ{tr [^_Ít& = "= f L& 1ɺ rAt& ` WUfK @ I QP S U@ C@ P Q [^_Í K @ I QP S( o@ C@ P Q S 2@ C@ P Q S @ C@ P Q 1ɺ$ ʣt& غ 貣ع 衣1ɉغ$ 蓣ع 肣ع qع `ع Oع > 0v 1ɺ Mt& 1ɺ$ 5t& 1ɺ$
t& VSË @ ~ Ptn1ɺ 询1ɺ 衢 萢1ɺ 肢 q ` {P _ ~ P 1ɺ #{ ~ Ptع {P D 8 ~ P 螡{ F - wh1ɺ R{th ~ P 1ɺ( "{ [^f1ɺ {uK @ I QP S _@ C@ P Q ~ P41ɺ% V{4K @ I QPR S @ C@ P& Q S @ C@ P QK @ I QP S V@ C@ P Q S @ C@ P Q [^ËK@ I QP K @ I QP S =@ C@ P Q ~ P1ɺ 5{K @ I QP S @ C@ P Q S @ C@ P Q lK @ I QP S @ C@ P Q S n@ C@ P Q S 1@ C@ P QK @ I QP S @ C@ P Q S @ C@ P& Q S O@ C@ P ?Q t& K@ I QP S @ C@ P Q S F@ C@ P Q S @ C@ P QK @ I QP S @ C@ P Q S d@ C@ P Q S '@ C@ P Q 8 ~ P 蚙t& W? V SË @ r1ɺ
d S B1ɺ 4 #1ɺ ~ Pb 1ɺ ۘ ʘ ع 蹘 { ta ~ P 1ɺ z{u'K @ I QP [^_f1
t& @ C@ P ?Qu S考 P@ C@ P Q ~ P%1ɺ 蟗 f1ɺ 芗t& SÃxt [Ë K @ I QP K @ I QP S u@ C@ P Q S L@ C@ P Q [ÐVSË @ x P# 1ɺ U {P t8088 [^Ív K@ I QP S u@ C@ P QK @ I QP S +@ C@ P Q S @ C@ P Q S0 @ C@ P Q S t1 @ C@ P Qu S %@ C@ P Q S @ C@ P Q S8 @ C@ P Q S n1
& @ C@ P Qu S8 @ C@ P Q S @ C@ P Q S @ C@ P Q S b@ C@ PDDQ [^f /v ' VSË {@ P tO( ~ P 1ɺ ۑ{ [^Ë@ KI QP S z@ C@ P Q ~ PO1ɺ *{OK @ I QP$q* S @ C@ P @Q S @ C@ P@ Q S @ C@ P Q S _@ C@ P Q S "@ C@ P Q [^Í& U W`> VSË @ F Pt- f g F - 1ɺ @ /1ɺ ! 1ɺ 1ɺ Ҏ 1ɺ 賎 袎1ɺ 蔎F _Z = 1ɺ
i X G 6ع %F - D 1ɺ 1ɺ ֍h ō1ɺ 跍 覍1ɺ 蘍 臍 v1ɺ hع WF - ^ 1ɺ
8 ' 1ɺ Ռ Č 賌1ɺ 襌h 蔌 背1ɺ u g1ɺ Yع HF - &~ P 1ɺ 1ɺ ދ1ɺ Ћ 迋1ɺ 豋h 蠋1ɺ 蒋 聋 p1ɺ b Q1ɺ C 21ɺ $ 1ɺ 1ɺ ؊1ɉغ ʊF - 1ɺ( 諊 蚊 艊1ɺ {h j Y H 7 &1ɺ 1ɺ Ɖ1ɺ 踉@ 觉 薉1ɺ 舉 w1ɉغ iF - J1ɺ < +h 1ɺ 1ɺ ܈1ɺ Έ 轈 謈 蛈ع 芈F - 1ɺ k Z1ɺ Lh ;ع *F - i 1ɺ 1ɺ ~ J ч1ɺ Ç 貇1ɺ 複 蓇1ɺ 腇 t1ɉغ fF - wq ع HF _vqP 1[ ^_] & ~ P1ɺ f ع ׆F _w1[ ^_]鷆& 1ɺ 袆~ h 脆& 1ɺ jt& [^_]Ív Gf /fع 1ɺ t& 1f ׅf1ɉغ
ع 豅ع 蠅ع 菅ع ~ع m1ɺ _Ff GfVSË @ ~ 3}~ Pth1ɺ [^i~ ~01ɺ
ڄ3謗5[^ t& 1ɺ 誄Ή1ɺ 蚄[^UWVSÃ @ E@ ? } D$ E = = = Pu1ɺ E = a = = P 蛊} Pp 1ɺ 賃1* )D$ v |$F E = i = @ = PD t& ߿ 1ɺ h 1ɺ ع߿ )9D$sljD$F E = u = = P ? w1ɺ i X1ɺ JÂ\U. );D$vljD$F
ft!ЉD$t$ߍ$uߋ V);D$t$Gf1 D$ M D$ +D$9Gut$ E - 1ɺ ;41ɺP & عh E - &E = p = = = 7 1ɺm 蹀10 )D$ v |$F 袅 )9D$sljD$F }
1ɺ6 G )9D$sljD$F1ɉ z )9D$sljD$F E = l = 1ɺz
? 1ɺ ع )9D$sljD$F1ɉ Uh D1ɺ 6߿ %1ɉغ E - . 1ɺ ~߿ ~1ɉغ ~E - 1ɺ ~ |$ t!ЉD$t$臊$uߋ |$ )9D$sljD$F 1ɺ F~D$m D$t D${ D$ )9D$sljD$F } W D$ D$ D$@ D$ D$ D$ g )9D$BD?S C C;C Q 4kPSK ;S + ` sPSKux;S <kPSKuV;S {CSu6;C sPSKu;S P C[^_]Ð1ɺ |Rt& v = t= t= S& 1ɺ J|9t& `t& t& ot& Qt& 6t& t& Ht& $t& = t= = s1ɺ {`= t= tz= & 1ɺ b{+} P1ɺ
C{ = t= f = 1ɺ|
{1ɺ z#t& zf zfyD$gD$UD$~Cr ع gz1ɺ YzWt& 1ɺ Bz1t& 1ɺ|
*zrt& 1ɺk zt& 1ɺ yt& 1ɺ yt& 1ɺ
y=t& 1ɺz
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y
t& 1ɺe yt& 1ɺ jyt& 1ɺ
Ryt& av 1ɺ *ylt& 1ɺ yT t& ' UWVSÃ @ H A\vLL$, @h$$s D$, @h$ts D$ [^_]Í& $` C(D@KD @ EɋSu!C;C
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s9vD<́ @u߉́ u s9w SKC E@ǁE @ EuC;C 4SKCC$@ǁ @ EuC;C 4SKCC4M@ƁM @ E2 s;s F <KsS s 11C9ȉvB<Ł @u݉Ł u% C9ȉwv KS ;C KpsS| ;s KpsSX ;s o ` KpsS4 ;s K ` KpsS ;s ' p KpsS s$tg11& C9ȉvB<Ł @u݉Ł u% C9ȉwv KSu|;C ` KpsSu\;s s J P KpsSu<;s S p KpsSu ;s 3 p SKCC0 @ǁ @ EuC;C 4SKCC,M@ƁM @ E s;s <KsS s( 11& C9ȉvB<Ł @u݉Ł u% C9ȉwv KSu\;C + p KpsSu<;s @ P KpsSu ;s P SKCC(@Ɓ @ Er s;s <{FCSO ;C p KFCS+ ;C h p Cs{ s,& 11 C9ЉvB Ł @u݉Ł u% C9Љwv k{ ;C p sPSKǃ ǃ d ;S {PSK@ ;S s ` P{SsC
;S 3
sPSKǃ @ ǃ @ u6;S @ sCSu;C ` Cؿ @C K @ ES s;s <SFCK ;C k p SFCK ;C G p SFC K ;C SsK~ ;s ` SFCKZ ;C SFCK6 ;C SFCK ;C SFCK ;C e P SsK s0te11t& C9ЉvB<Ł @u݉Ł u% C9Љwv SKu\;C p SpsKu<;s p SpsKu ;s p KSCC4@Ɓ @ E s;s T <KFCS ;C 4
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NVReadVgaCrtc nvReadMC NVWriteVgaCrtc reg_debug tv_norm tv_disable override_conntype nofbaccel noaccel ignorelid uscript_tmds uscript_lvds duallink vram_notify vram_pushbuf vbios modeset noagp ctxfw H 8 ` H 0 X nouveau_card_takedown nouveau_load nouveau_card_init nouveau_channel_cleanup nouveau_channel_free nouveau_channel_alloc @ nouveau_gpuobj_channel_takedown nouveau_gpuobj_channel_init nouveau_gpuobj_channel_init_pramin nouveau_gpuobj_gr_new nouveau_gpuobj_dma_new nouveau_gpuobj_new_fake nouveau_gpuobj_ref_del nouveau_ramht_remove nouveau_ramht_hash_handle nouveau_gpuobj_ref_add nouveau_ramht_insert nouveau_gpuobj_del nouveau_gpuobj_late_takedown nouveau_gpuobj_takedown nouveau_gpuobj_init nouveau_gpuobj_early_init nouveau_gpuobj_new nouveau_ratelimit nouveau_pgraph_intr_context_switch nouveau_notifier_gpuobj_dtor nouveau_sgdma_destroy nouveau_sgdma_unbind nouveau_sgdma_bind nouveau_sgdma_clear nouveau_sgdma_populate nouveau_bo_del_ttm validate_init nouveau_ttm_global_init NVWriteRAMDAC nvWriteVIDEO nvWriteMC NVReadRAMDAC NVWriteVgaCrtc NVWriteCRTC NVWritePRMVIO NVReadVgaCrtc NVWriteVgaAttr NVReadPRMVIO NVReadVgaAttr NVReadCRTC nvReadMC nvReadFB nvReadEXTDEV h Ɠ Ɠ x Ɠ Ɠ Ɠ Ɠ Ɠ Ɠ Ɠ x p 8 p 8 p X X nvReadMC nvWriteMC NVReadVgaCrtc NVWriteVgaCrtc P 2 z 3 p 4 `
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nv50_graph_load_context nv50_graph_destroy_context nv50_graph_create_context nv50_graph_takedown nv50_graph_init nv50_graph_init_reset nv50_graph_init_regs__nv nv50_graph_init_regs nv50_graph_init_intr nv50_graph_init_ctxctl Q K K K K K Q K K Q K Q Q K Q K K K K K K K K K K K K K K K K K K K K K K K K Q Q jQ Q jQ jQ jQ Q jQ Q jQ Q jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ jQ Q q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q r 0q q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q 0q r 0q r 0q r 0q q 0q 0q 0q 0q 0q 0q 0q q 0q 0q q 0q q 0q 0q q 0q q 0q q 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p Z Z Z Z Z p p p p p p ` p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p h p P p p p p p p p p p p p 8 p p 8 p 8 p p p p p p p p p p p p p p | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nv04_instmem_determine_amount nv04_instmem_configure_fixed_tables nv50_instmem_bind nv50_instmem_takedown nv50_instmem_init * % % % % % % + * % % % % % % % + % % % % % (& % + ` P! @ = P; P 0? 1 nv50_crtc_create nv50_crtc_lut_load nv50_crtc_do_mode_set_base nv50_crtc_mode_set nv50_crtc_commit nv50_crtc_prepare nv50_crtc_destroy nv50_crtc_set_scale nv50_crtc_set_dither nv50_crtc_blank pY PW pT @T X T 0T `[ T nv50_dac_create nv50_dac_detect nv50_dac_mode_set nv50_dac_mode_fixup nv50_dac_dpms nv50_dac_destroy nv50_dac_disconnect a b `_ 0_ _ _ _ @d nv50_sor_create nv50_sor_mode_set nv50_sor_mode_fixup nv50_sor_dpms nv50_sor_dp_link_train nv50_sor_destroy nv50_sor_disconnect nv50_cursor_fini nv50_cursor_show nv50_cursor_hide nv50_cursor_set_offset nv50_display_irq_handler nv50_display_irq_handler_bh nv50_display_irq_head nv50_display_unk20_handler nv50_display_destroy nv50_display_disable nv50_display_create nv50_display_init P P ` P P ` @ nv04_dac_destroy NVReadVgaCrtc NVReadRAMDAC NVWriteRAMDAC NVWriteVgaCrtc nvReadMC nvWriteMC ` 0 P 0 P nv04_dfp_destroy NVReadRAMDAC NVWriteRAMDAC nv04_dfp_mode_set nvReadEXTDEV NVWriteVgaCrtc NVReadVgaCrtc nvReadMC NVWriteVgaCrtc NVWriteRAMDAC @ X 8 NVReadRAMDAC NVWriteRAMDAC nv17_tv_destroy NVWriteRAMDAC 0; : 1 . . 3 PH < B . @L > . NVWriteRAMDAC NVWriteCRTC NVWriteVgaCrtc nv_crtc_mode_set NVReadVgaCrtc NVReadCRTC nv_crtc_calc_state_ext NVReadRAMDAC nv_crtc_dpms nv_crtc_destroy NVReadVgaCrtc nvReadMC NVWriteVgaCrtc nv04_display_destroy nv04_display_create NVWriteVgaCrtc NVReadRAMDAC NVWriteRAMDAC NVReadCRTC NVWriteCRTC ` HMM~_ 2 3 6 7 Bm n n x ! $ ' i * 4 - 4 0 E 3 F 6 T 9 # < ", ? ; B ]< E
> H l> K ? N L Q Fb T m W cr Z ]
` c f i l / o r 8 u x = { ~ n .4 B +[ Y[ ^ I_ t_ ab b p r u U} <7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<6>[drm] nouveau %s: We're back, enabling device...
<6>[drm] nouveau %s: POSTing device...
<3>[drm] nouveau %s: error reinitialising AGP: %d
<6>[drm] nouveau %s: Reinitialising engines...
<6>[drm] nouveau %s: Restoring GPU objects...
<6>[drm] nouveau %s: Restoring mode...
<7>[drm] nouveau %s: %s: reg %08x val %08x
<6>[drm] nouveau %s: Disabling fbcon acceleration...
<6>[drm] nouveau %s: Unpinning framebuffer(s)...
<6>[drm] nouveau %s: Evicting buffers...
<6>[drm] nouveau %s: Idling channels...
<3>[drm] nouveau %s: Failed to idle channel %d for suspend
<6>[drm] nouveau %s: Suspending GPU objects...
<3>[drm] nouveau %s: ... failed: %d
<6>[drm] nouveau %s: And we're gone!
<6>[drm] nouveau %s: Re-enabling acceleration..
<3>[drm] nouveau %s: NV%02x unsupported
<7>[drm] nouveau %s: %s:%d - prev state = %d
<3>VGA switcheroo: switched nouveau on
<3>VGA switcheroo: switched nouveau off
<3>[drm] nouveau %s: Error %d registering backlight
<7>[drm] nouveau %s: %s:%d - vendor: 0x%X device: 0x%X class: 0x%X
<3>[drm] nouveau %s: Unable to initialize the mmio mapping. Please report your setup to dri-devel@lists.sourceforge.net
<7>[drm] nouveau %s: %s:%d - regs mapped ok at 0x%llx
<6>[drm] nouveau %s: Unsupported chipset 0x%08x
<6>[drm] nouveau %s: Detected an NV%2x generation card (0x%08x)
<3>[drm] nouveau %s: Failed to init RAMIN mapping, limited instance memory available
<3>[drm] nouveau %s: Failed to map BAR0 PRAMIN.
<3>[drm] nouveau %s: called without init
<3>[drm] nouveau %s: Requested PCIGART address, while no PCIGART was created
<3>[drm] nouveau %s: unknown parameter %lld
<3>[drm] nouveau %s: PGRAPH idle timed out with status 0x%08x
<3>[drm] nouveau %s: Error referencing pushbuf ctxdma: %d
<6>[drm] nouveau %s: %s: freeing fifo %d
<3>[drm] nouveau %s: Failed to idle channel %d.
<6>[drm] nouveau %s: Allocating FIFO number %d
<3>[drm] nouveau %s: error allocating DMA push buffer: %d
<3>[drm] nouveau %s: error pinning DMA push buffer: %d
<3>[drm] nouveau %s: pushbuf %d
<3>[drm] nouveau %s: ioremap of regs failed.
<3>[drm] nouveau %s: gpuobj %d
<3>[drm] nouveau %s: pbctxdma %d
<6>[drm] nouveau %s: %s: initialised FIFO %d
<3>[drm] nouveau %s: called without init
<3>[drm] nouveau %s: pid %d doesn't own channel %d
<7>[drm] nouveau %s: %s:%d - clearing FIFO enables from file_priv
<3>[drm] nouveau %s: no bridge device
<3>[drm] nouveau %s: impossible!
<3>[drm] nouveau %s: timeout: (0x100c80 & 1) == 0 (2)
<3>[drm] nouveau %s: 0x100c80 = 0x%08x
<6>[drm] nouveau %s: Detected %dMiB VRAM
<6>[drm] nouveau %s: Stolen system memory at: 0x%010llx
<3>[drm] nouveau %s: Unable to acquire AGP: %d
<3>[drm] nouveau %s: Unable to get AGP info: %d
<3>[drm] nouveau %s: Unable to enable AGP: %d
<3>[drm] nouveau %s: Error setting DMA mask: %d
<3>[drm] nouveau %s: Error initialising bo driver: %d
<3>[drm] nouveau %s: Failed VRAM mm init: %d
<4>[drm] nouveau %s: failed to reserve VGA memory
<3>[drm] nouveau %s: Error initialising AGP: %d
<3>[drm] nouveau %s: Error initialising PCI(E): %d
<6>[drm] nouveau %s: %d MiB GART (aperture)
<3>[drm] nouveau %s: Failed TT mm init: %d
<7>[drm] nouveau %s: %s:%d - ch%d handle=0x%08x
<7>[drm] nouveau %s: %s:%d - hash=0x%08x
<3>[drm] nouveau %s: Channel mismatch: obj %d, ref %d
<3>[drm] nouveau %s: AII, no VRAM backing gpuobj
<3>[drm] nouveau %s: No hash table!
<7>[drm] nouveau %s: %s:%d - insert ch%d 0x%08x: h=0x%08x, c=0x%08x
<7>[drm] nouveau %s: %s:%d - collision ch%d 0x%08x: h=0x%08x
<3>[drm] nouveau %s: RAMHT space exhausted. ch=%d
<7>[drm] nouveau %s: %s:%d - remove ch%d 0x%08x: h=0x%08x, c=0x%08x
<3>[drm] nouveau %s: RAMHT entry not found. ch=%d, handle=0x%08x
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - gpuobj %p
<3>[drm] nouveau %s: gpuobj refcount is %d
<3>[drm] nouveau %s: gpuobj %p still exists at takedown, refs=%d
<7>[drm] nouveau %s: %s:%d - ch%d size=%u align=%d flags=0x%08x
<7>[drm] nouveau %s: %s:%d - private heap
<7>[drm] nouveau %s: %s:%d - global heap fallback
<7>[drm] nouveau %s: %s:%d - global heap
<3>[drm] nouveau %s: No PRAMIN heap!
<7>[drm] nouveau %s: %s:%d - ch%d h=0x%08x gpuobj=%p
<7>[drm] nouveau %s: %s:%d - ref %p
<7>[drm] nouveau %s: %s:%d - ch%d
<7>[drm] nouveau %s: %s:%d - ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x
<3>[drm] nouveau %s: Error allocating channel PRAMIN: %d
<3>[drm] nouveau %s: Error creating PRAMIN heap: %d
<7>[drm] nouveau %s: %s:%d - p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x
<7>[drm] nouveau %s: %s:%d - ch%d class=0x%04x offset=0x%llx size=0x%llx
<7>[drm] nouveau %s: %s:%d - access=%d target=%d
<3>[drm] nouveau %s: Error creating gpuobj: %d
<3>[drm] nouveau %s: obj offset exceeds 32-bits
<3>[drm] nouveau %s: Invalid GART type %d
<7>[drm] nouveau %s: %s:%d - ch%d class=0x%04x
<7>[drm] nouveau %s: %s:%d - ch%d vram=0x%08x tt=0x%08x
<3>[drm] nouveau %s: init pramin
<3>[drm] nouveau %s: Error creating VRAM ctxdma: %d
<3>[drm] nouveau %s: Error referencing VRAM ctxdma: %d
<3>[drm] nouveau %s: Error creating TT ctxdma: %d
<3>[drm] nouveau %s: Error referencing TT ctxdma: %d
<3>[drm] nouveau %s: called without init
<3>[drm] nouveau %s: pid %d doesn't own channel %d
<3>[drm] nouveau %s: Error creating object: %d (%d/0x%08x)
<3>[drm] nouveau %s: Error referencing object: %d (%d/0x%08x)
<3>[drm] nouveau %s: Illegal object class: 0x%x
<6>[drm] nouveau %s: %s - nSource: <6>[drm] nouveau %s: %s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_MP_EXEC - TP %d MP %d: at %06x warp %d, opcode %08x %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_MP_EXEC - TP %d: No MPs claiming errors?
<6>[drm] nouveau %s: %s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d
<6>[drm] nouveau %s: %s - no VM fault?
<3>[drm] nouveau %s: magic set %d:
<3>[drm] nouveau %s: 0x%08x: 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x
<6>[drm] nouveau %s: %s - TP%d: Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: %s - No TPs claiming errors?
<3>[drm] nouveau %s: AIII, invalid/inactive channel id %d
<6>[drm] nouveau %s: PGRAPH_TRAP - no units reporting traps?
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH - no ustatus?
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?
<6>[drm] nouveau %s: PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_M2MF - no ustatus?
<6>[drm] nouveau %s: PGRAPH_TRAP_M2MF - %08x %08x %08x %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_VFETCH - no ustatus?
<6>[drm] nouveau %s: PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_STRMOUT - no ustatus?
<6>[drm] nouveau %s: PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_CCACHE - no ustatus?
<6>[drm] nouveau %s: PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x
<6>[drm] nouveau %s: PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x
<6>[drm] nouveau %s: PGRAPH_TRAP - Unknown trap 0x%08x
<7>[drm] nouveau %s: %s:%d - PGRAPH context switch interrupt channel %x
<3>[drm] nouveau %s: Context switch not implemented
<6>[drm] nouveau %s: Unhandled PGRAPH_INTR - 0x%08x
<6>[drm] nouveau %s: PGRAPH_DATA_ERROR - <6>[drm] nouveau %s: PFIFO_CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x
<6>[drm] nouveau %s: PFIFO_DMA_PUSHER - Ch %d
<6>[drm] nouveau %s: PFIFO_INTR 0x%08x - Ch %d
<6>[drm] nouveau %s: PFIFO still angry after %d spins, halt
<3>[drm] nouveau %s: Unhandled PMC INTR status bits 0x%08x
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: Channel %d doesn't have a notifier heap!
<3>[drm] nouveau %s: Channel %d notifier block full
<3>[drm] nouveau %s: Bad DMA target, mem_type %d!
<3>[drm] nouveau %s: Error creating notifier ctxdma: %d
<3>[drm] nouveau %s: Error referencing notifier ctxdma: %d
<3>[drm] nouveau %s: called without init
<3>[drm] nouveau %s: pid %d doesn't own channel %d
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - num_pages = %ld
<3>[drm] nouveau %s: timeout: (0x100c80 & 1) == 0 (2)
<3>[drm] nouveau %s: 0x100c80 = 0x%08x
<7>[drm] nouveau %s: %s:%d - pg=0x%lx
<3>[drm] nouveau %s: Error creating sgdma object: %d
<3>[drm] nouveau %s: Unimplemented on NV50
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_dma.c <3>[drm] nouveau %s: Unknown GART type: %d
<3>[drm] nouveau %s: Unsupported memory type %u
<3>[drm] nouveau %s: Unknown GART type %d
<3>[drm:%s] *ERROR* bo %p still attached to GEM object
<3>[drm] nouveau %s: bo %p pinned elsewhere: 0x%08x vs 0x%08x
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_bo.c /usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_fence.c <3>[drm] nouveau %s: fail wait other chan
<3>[drm] nouveau %s: fail set_domain
<3>[drm] nouveau %s: fail ttm_validate
<3>[drm] nouveau %s: %s failed and gave up.
<3>[drm] nouveau %s: Unknown handle 0x%08x
<3>[drm] nouveau %s: multiple instances of buffer %d on validation list
<3>[drm] nouveau %s: fail reserve
<3>[drm] nouveau %s: invalid valid domains: 0x%08x
<3>[drm] nouveau %s: bo %p mapped by process trying to validate it!
<3>[drm] nouveau %s: fail wait_cpu
<3>[drm] nouveau %s: validate_init
<3>[drm] nouveau %s: validate vram_list
<3>[drm] nouveau %s: validate gart_list
<3>[drm] nouveau %s: validate both_list
<3>[drm] nouveau %s: reloc bo index invalid
<3>[drm] nouveau %s: reloc container bo index invalid
<3>[drm] nouveau %s: reloc outside of bo
<3>[drm] nouveau %s: failed kmap for reloc
<3>[drm] nouveau %s: reloc wait_idle failed: %d
<3>[drm] nouveau %s: called without init
<3>[drm] nouveau %s: pid %d doesn't own channel %d
<3>[drm] nouveau %s: bad page flags: 0x%08x
<3>[drm] nouveau %s: pushbuf push count exceeds limit: %d max %d
<3>[drm] nouveau %s: pushbuf bo count exceeds limit: %d max %d
<3>[drm] nouveau %s: pushbuf reloc count exceeds limit: %d max %d
<3>[drm] nouveau %s: validate: %d
<3>[drm] nouveau %s: reloc apply: %d
<6>[drm] nouveau %s: nv50cal_space: %d
<3>[drm] nouveau %s: cal_space: %d
<3>[drm] nouveau %s: jmp_space: %d
<3>[drm] nouveau %s: error fencing pushbuf: %d
<3>[drm:%s] *ERROR* Failed setting up TTM memory accounting
<3>[drm:%s] *ERROR* Failed setting up TTM BO subsystem
<7>[drm] nouveau %s: %s: head %d reg %08x val %02x
<7>[drm] nouveau %s: %s: reg %08x val %08x
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<4>[drm] nouveau %s: VPLL %d outwith limits, attempting to fix
<6>[drm] nouveau %s: %sing VGA fonts
<3>[drm] nouveau %s: Failed to map VRAM, cannot save/restore VGA fonts.
<7>[drm] nouveau %s: %s: reg %08x val %08x
<3>[drm] nouveau %s: Could not find a compatible set of PLL values
<5>[drm] nouveau %s: ... BIOS signature not found
<5>[drm] nouveau %s: ... BIOS checksum invalid
<6>[drm] nouveau %s: ... appears to be valid
<6>[drm] nouveau %s: BIT table '%c' not found
<3>[drm] nouveau %s: Do not understand BIT U table
<3>[drm] nouveau %s: Do not understand BIT TMDS table
<3>[drm] nouveau %s: Pointer to TMDS table invalid
<4>[drm] nouveau %s: TMDS table revision %d.%d not currently supported
<4>[drm] nouveau %s: TMDS table script pointers not stubbed
<3>[drm] nouveau %s: Do not understand BIT LVDS table
<3>[drm] nouveau %s: Do not understand init table
<3>[drm] nouveau %s: Do not understand BIT display table
<3>[drm] nouveau %s: Do not understand BIT C table
<3>[drm] nouveau %s: Do not understand BIT A table
<3>[drm] nouveau %s: Pointer to BIT loadval table invalid
<3>[drm] nouveau %s: BIT loadval table version %d.%d not supported
<3>[drm] nouveau %s: Do not understand BIT loadval table
<3>[drm] nouveau %s: BIT i table too short for needed information
<6>[drm] nouveau %s: Bios version %02x.%02x.%02x.%02x
<4>[drm] nouveau %s: BIT i table not long enough for DAC load detection comparison table
<4>[drm] nouveau %s: DAC load detection comparison table version %d.%d not known
<6>[drm] nouveau %s: BMP version %d.%d
<3>[drm] nouveau %s: You have an unsupported BMP version. Please send in your bios
<3>[drm] nouveau %s: Bad BMP checksum
<6>[drm] nouveau %s: BIT BIOS found
<6>[drm] nouveau %s: BMP BIOS found
<3>[drm] nouveau %s: No known BIOS signature found
<3>[drm] nouveau %s: Unknown LVDS configuration bits, please report
<4>[drm] nouveau %s: DCB I2C table version mismatch (%02X vs %02X)
<4>[drm] nouveau %s: DCB I2C table has more entries than indexable (%d entries, max %d)
<3>[drm] nouveau %s: DCB I2C index too big (%d >= %d)
<3>[drm] nouveau %s: DCB I2C entry invalid
<4>[drm] nouveau %s: DCB I2C table has port type %d
<6>[drm] nouveau %s: Merging DCB entries %d and %d
<4>[drm] nouveau %s: Invalid DCB GPIO table entry length.
<4>[drm] nouveau %s: Too many entries in the DCB GPIO table.
<7>[drm] nouveau %s: No DCB connector table present
<6>[drm] nouveau %s: DCB connector table: VHER 0x%02x %d %d %d
<3>[drm] nouveau %s: Unknown! Please report.
<6>[drm] nouveau %s: %d: 0x%08x: type 0x%02x idx %d tag 0x%02x
<4>[drm] nouveau %s: unknown type, using 0x%02x
<4>[drm] nouveau %s: -> type 0x%02x
<3>[drm] nouveau %s: ======= misaligned reg 0x%08X =======
<4>[drm] nouveau %s: === C51 misaligned reg 0x%08X not verified ===
<3>[drm] nouveau %s: === reg 0x%08x out of mapped bounds ===
<7>[drm] nouveau %s: 0x%04X: [ (0x%02X) - %s ]
<3>[drm] nouveau %s: 0x%04X: Init table command not found: 0x%02X
<4>[drm] nouveau %s: Offset 0x%04X greater than known bios image length. Corrupt image?
<4>[drm] nouveau %s: More than %d opcodes to a table is unlikely, is the bios image corrupt?
<6>[drm] nouveau %s: Parsing VBIOS init table %d at offset 0x%04X
<7>[drm] nouveau %s: 0x%04X: ------ Executing following commands ------
<3>[drm] nouveau %s: ========== unknown indexed io port 0x%04X ==========
<7>[drm] nouveau %s: 0x%04X: ---- Executing following commands ----
<7>[drm] nouveau %s: 0x%04X: Calling script %d
<7>[drm] nouveau %s: 0x%04X: End of script %d
<7>[drm] nouveau %s: 0x%04X: Executing subroutine at 0x%04X
<7>[drm] nouveau %s: 0x%04X: End of 0x%04X subroutine
<7>[drm] nouveau %s: 0x%04X: ------ Skipping following commands ------
<7>[drm] nouveau %s: 0x%04X: Repeating following segment %d times
<3>[drm] nouveau %s: Unknown DCB subtype 4/%d
<3>[drm] nouveau %s: Unknown DCB type %d
<3>[drm] nouveau %s: Pointer to LVDS manufacturer table invalid
<3>[drm] nouveau %s: LVDS table header not understood
<3>[drm] nouveau %s: LVDS table revision %d.%d not currently supported
<6>[drm] nouveau %s: Attempting to use BIOS image from %s
<3>[drm] nouveau %s: VBIOS source '%s' invalid
<6>[drm] nouveau %s: Attempting to load BIOS image from %s
<6>[drm] nouveau %s: Using BIOS image from %s
<3>[drm] nouveau %s: No valid BIOS image found
<4>[drm] nouveau %s: No output data (DCB) found in BIOS
<6>[drm] nouveau %s: Assuming a CRT output exists
<3>[drm] nouveau %s: Bad Display Configuration Block signature (%08X)
<3>[drm] nouveau %s: Bad Display Configuration Block signature (%s)
<5>[drm] nouveau %s: No useful information in BIOS output table; adding all possible outputs
<4>[drm] nouveau %s: No pointer to DCB I2C port table
<5>[drm] nouveau %s: Raw DCB entry %d: %08x %08x
<6>[drm] nouveau %s: Found Display Configuration Block version %d.%d
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_bios.c <7>[drm] nouveau %s: 0x%04X: Sleeping for 0x%04X microseconds
<7>[drm] nouveau %s: Read: Reg: 0x%08X, Data: 0x%08X
<7>[drm] nouveau %s: 0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X
<7>[drm] nouveau %s: 0x%04X: Checking if 0x%08X equals 0x%08X
<7>[drm] nouveau %s: 0x%04X: Condition: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Condition fulfilled -- continuing to execute
<7>[drm] nouveau %s: 0x%04X: Condition not fulfilled -- skipping following commands
<7>[drm] nouveau %s: 0x%04X: Condition: 0x%02X, Retries: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Condition met, continuing
<7>[drm] nouveau %s: 0x%04X: Condition not met, sleeping for 20ms
<4>[drm] nouveau %s: 0x%04X: Condition still not met after %dms, skipping following opcodes
<7>[drm] nouveau %s: Write: Reg: 0x%08X, Data: 0x%08X
<3>[drm] nouveau %s: 0x%04X: Zero block length - has the M table been parsed?
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X
<7>[drm] nouveau %s: 0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X
<7>[drm] nouveau %s: 0x%04X: BaseReg: 0x%08X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Address: 0x%02X, Data: 0x%02X
<3>[drm] nouveau %s: INIT_GPIO on unsupported chipset
<7>[drm] nouveau %s: 0x%04X: Entry: 0x%08X
<7>[drm] nouveau %s: Indexed IO write: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<3>[drm] nouveau %s: Too few entries in HW sequencer table for requested entry
<3>[drm] nouveau %s: Unknown HW sequencer entry size
<6>[drm] nouveau %s: Loading NV17 power sequencing microcode
<7>[drm] nouveau %s: 0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X
<3>[drm] nouveau %s: ========== unknown io port 0x%04X ==========
<7>[drm] nouveau %s: %s: head %d reg %08x val %02x
<7>[drm] nouveau %s: IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: %s: reg %08x val %08x
<6>[drm] nouveau %s: 0x%04X: Parsing digital output script table
<3>[drm] nouveau %s: Pixel clock comparison table not found
<3>[drm] nouveau %s: LVDS output init script not found
<3>[drm] nouveau %s: CR58 doesn't have a valid DCB entry currently (%02X)
<3>[drm] nouveau %s: Magic Lookup Value too big (%02X)
<7>[drm] nouveau %s: 0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, Mask: 0x%02X, Data: 0x%02X
<3>[drm] nouveau %s: INIT_ZM_AUXCH: no active output
<3>[drm] nouveau %s: INIT_ZM_AUXCH: couldn't get auxch %d
<3>[drm] nouveau %s: INIT_ZM_AUXCH: wr auxch fail %d
<3>[drm] nouveau %s: INIT_AUXCH: no active output
<3>[drm] nouveau %s: INIT_AUXCH: couldn't get auxch %d
<3>[drm] nouveau %s: INIT_AUXCH: rd auxch fail %d
<3>[drm] nouveau %s: INIT_AUXCH: wr auxch fail %d
<7>[drm] nouveau %s: 0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Data: 0x%02X
<7>[drm] nouveau %s: 0x%04X: I2CReg: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: 0x%04X: I2CReg: 0x%02X, Value: 0x%02X, Mask: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: Indexed IO read: Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: 0x%04X: IO condition: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Checking if 0x%02X equals 0x%02X
<7>[drm] nouveau %s: 0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, Cmpval: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X
<3>[drm] nouveau %s: 0x%04X: Config 0x%02X exceeds maximal bound 0x%02X
<7>[drm] nouveau %s: 0x%04X: Writing config %02X
<7>[drm] nouveau %s: 0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X
<3>[drm] nouveau %s: Pointer to flat panel table invalid
<3>[drm] nouveau %s: FP table revision %d.%d not currently supported
<3>[drm] nouveau %s: Pointer to flat panel xlat table invalid
<3>[drm] nouveau %s: Bad flat panel table index
<6>[drm] nouveau %s: BIOS FP mode: %dx%d (%dkHz pixel clock)
<6>[drm] nouveau %s: Calling LVDS script %d:
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<3>[drm] nouveau %s: LVDS table revision not currently supported
<3>[drm] nouveau %s: No pointer to DisplayPort table
<3>[drm] nouveau %s: DisplayPort table version 0x%02x unknown
<3>[drm] nouveau %s: TMDS output init script not found
<3>[drm] nouveau %s: Pointer to PLL limits table invalid
<3>[drm] nouveau %s: PLL limits table revision 0x%X not currently supported
<4>[drm] nouveau %s: Default PLL limit entry has non-zero register field
<7>[drm] nouveau %s: Loading PLL limits for reg 0x%08x
<4>[drm] nouveau %s: Max log2 P value greater than 7 (%d)
<4>[drm] nouveau %s: Bits set in PLL configuration byte (%x)
<7>[drm] nouveau %s: Loading PLL limits for register 0x%08x
<3>[drm] nouveau %s: Register 0x%08x not found in PLL limits table <3>[drm] nouveau %s: PLL limits table not version 3.x
<7>[drm] nouveau %s: 0x%04X: Type %02x Reg 0x%08x Freq %dKHz
<3>[drm] nouveau %s: PLL type 0x%02x not found in PLL limits table <7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, Freq: %d0kHz
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%04X, Freq: %dkHz
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz
<7>[drm] nouveau %s: 0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, Shift: 0x%02X, IO Flag Condition: 0x%02X, Count: 0x%02X, Reg: 0x%08X
<7>[drm] nouveau %s: 0x%04X: Condition fulfilled -- frequency doubled
<7>[drm] nouveau %s: 0x%04X: Condition not fulfilled -- frequency unchanged
<7>[drm] nouveau %s: 0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz
<6>[drm] nouveau %s: Found EDID in BIOS
<3>[drm] nouveau %s: No pointer to output script table
<3>[drm] nouveau %s: Output script table version 0x%02x unknown
<7>[drm] nouveau %s: Searching for output entry for %d %d %d
<3>[drm] nouveau %s: Couldn't find matching output script table
<3>[drm] nouveau %s: Table 0x%04x not found for %d/%d, using first
<7>[drm] nouveau %s: output script 0 not found
<6>[drm] nouveau %s: 0x%04X: parsing output script 0
<7>[drm] nouveau %s: output script 1 not found
<6>[drm] nouveau %s: 0x%04X: parsing output script 1
<7>[drm] nouveau %s: output script 2 not found
<6>[drm] nouveau %s: 0x%04X: parsing output script 2
<3>[drm] nouveau %s: clock script 0 not found
<6>[drm] nouveau %s: 0x%04X: parsing clock script 0
<7>[drm] nouveau %s: clock script 1 not found
<6>[drm] nouveau %s: 0x%04X: parsing clock script 1
<6>[drm] nouveau %s: Parsing VBIOS init table at offset 0x%04X
<6>[drm] nouveau %s: Adaptor not initialised
<3>[drm] nouveau %s: Unable to POST this chipset
<6>[drm] nouveau %s: Running VBIOS init tables
INIT_RAM_RESTRICT_ZM_REG_GROUP INIT_ZM_REG_GROUP_ADDRESS_LATCHED <7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<3>[drm] nouveau %s: unknown i2c port %d
<3>[drm] nouveau %s: DCB I2C port type %d unknown
<3>[drm] nouveau %s: Failed to register i2c %d
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_connector.c <3>[drm] nouveau %s: can't find encoder to force %s on!
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - native mode from preferred
<7>[drm] nouveau %s: %s:%d - native mode from largest: %dx%d@%d
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<7>[drm] nouveau %s: %s: reg %08x val %08x
<3>[drm] nouveau %s: DDC responded, but no EDID for %s
<3>[drm] nouveau %s: Detected %s, but failed init
<3>[drm] nouveau %s: Detected %d encoder on %s, but no object!
<3>[drm] nouveau %s: Error parsing LVDS table, disabling LVDS
<3>[drm] nouveau %s: LVDS present in DCB table, but couldn't determine its native mode. Disabling.
<6>[drm] nouveau %s: Detected a VGA connector
<6>[drm] nouveau %s: Detected a TV connector
<6>[drm] nouveau %s: Detected a DVI-I connector
<6>[drm] nouveau %s: Detected a DVI-D connector
<6>[drm] nouveau %s: Detected a HDMI connector
<6>[drm] nouveau %s: Detected a LVDS connector
<6>[drm] nouveau %s: Detected a DisplayPort connector
<6>[drm] nouveau %s: Detected an eDP connector
<3>[drm] nouveau %s: unknown connector type: 0x%02x!!
<4>[drm] nouveau %s: no encoders, ignoring
<3>[drm] nouveau %s: failed to allocate framebuffer
<3>[drm] nouveau %s: failed to pin fb: %d
<3>[drm] nouveau %s: failed to map fb: %d
<3>[drm] nouveau %s: failed to allocate fb.
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_drv.h <6>[drm] nouveau %s: allocated %dx%d fb: 0x%lx, bo %p
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: GPU lockup - switching to software fbcon
<7>[drm] nouveau %s: %s:%d - ch %d cmd %d addr 0x%x len %d
<3>[drm] nouveau %s: expected bit 24 == 1, got 0x%08x
<7>[drm] nouveau %s: %s:%d - wr %d: 0x%08x
<3>[drm] nouveau %s: expected bit 16 == 0, got 0x%08x
<3>[drm] nouveau %s: auxch DEFER too many times, bailing
<7>[drm] nouveau %s: %s:%d - rd %d: 0x%08x
<3>[drm] nouveau %s: expected bit 24 == 0, got 0x%08x
<7>[drm] nouveau %s: %s:%d - encoder: link_bw %d, link_nr %d
display: link_bw %d, link_nr %d version 0x%02x
<7>[drm] nouveau %s: %s:%d - adjust 0x%02x 0x%02x
<7>[drm] nouveau %s: %s:%d - config 0x%02x 0x%02x 0x%02x 0x%02x
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_dp.c <7>[drm] nouveau %s: %s:%d - link training!!
<7>[drm] nouveau %s: %s:%d - begin train: bw %d, lanes %d
<7>[drm] nouveau %s: %s:%d - begin cr
<7>[drm] nouveau %s: %s:%d - status: 0x%02x 0x%02x
<7>[drm] nouveau %s: %s:%d - begin eq
<7>[drm] nouveau %s: %s:%d - we failed
<7>[drm] nouveau %s: %s:%d - retry link training at low rate
<3>[drm] nouveau %s: invalid auxch status: 0x%08x
<3>[drm] nouveau %s: No ctxprog for NV%02x
<3>[drm] nouveau %s: OOM copying ctxprog
<3>[drm] nouveau %s: ctxprog invalid
<3>[drm] nouveau %s: No ctxvals for NV%02x
<3>[drm] nouveau %s: OOM copying ctxvals
<3>[drm] nouveau %s: ctxvals invalid
<3>[drm] nouveau %s: Timeout flushing the PFIFO cache.
<3>[drm] nouveau %s: Inactive channel on PFIFO: %d
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - ch%d, nt=%d
<7>[drm] nouveau %s: %s:%d - ch%d
<3>[drm] nouveau %s: error creating thingo0: %d
<3>[drm] nouveau %s: error creating thingo1: %d
<3>[drm] nouveau %s: error enabling ch%d: %d
<3>[drm] nouveau %s: Inactive channel on PFIFO: %d
<7>[drm] nouveau %s: %s:%d - nv04_graph_context_create %d
<3>[drm] nouveau %s: unknow offset nv17_ctx_regs %d
<3>[drm] nouveau %s: unknow offset nv10_ctx_regs %d
<3>[drm] nouveau %s: incomplete pipe init for 0x%x : %p/%p
<7>[drm] nouveau %s: %s:%d - nv10_graph_context_create %d
<3>[drm] nouveau %s: Please contact the devs if you want your NV%x card to work
<3>[drm] nouveau %s: Failed: Instance=0x%08x Save=%d
<3>[drm] nouveau %s: IP: 0x%02x, Opcode: 0x%08x
<3>[drm] nouveau %s: 0x40030C = 0x%08x
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: Couldn't alloc ctxprog! Disabling acceleration.
<3>[drm] nouveau %s: Ctxprog is still running
<7>[drm] nouveau %s: %s:%d - ch%d
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_grctx.h /usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_grctx.h <3>[drm] nouveau %s: I don't know how to make a ctxprog for your NV%x card.
<3>[drm] nouveau %s: Disabling acceleration. Please contact the devs.
<7>[drm] nouveau %s: %s:%d - RAMHT offset=0x%x, size=%d
<7>[drm] nouveau %s: %s:%d - RAMRO offset=0x%x, size=%d
<7>[drm] nouveau %s: %s:%d - RAMFC offset=0x%x, size=%d
<7>[drm] nouveau %s: %s:%d - RAMIN size: %dKiB
<3>[drm] nouveau %s: Failed to init RAMIN heap
<7>[drm] nouveau %s: %s:%d - Rsvd VRAM base: 0x%08x
<7>[drm] nouveau %s: %s:%d - VBIOS image: 0x%08x
<7>[drm] nouveau %s: %s:%d - Aperture size: %d MiB
<7>[drm] nouveau %s: %s:%d - PT size: %d KiB
<7>[drm] nouveau %s: %s:%d - NV50VM: GART 0x%016llx-0x%016llx
<7>[drm] nouveau %s: %s:%d - NV50VM: VRAM 0x%016llx-0x%016llx
<3>[drm] nouveau %s: Error creating VRAM page tables: %d
<3>[drm] nouveau %s: Error reading back PRAMIN at 0x%08x
<3>[drm] nouveau %s: Failed to init RAMIN heap
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: error getting PRAMIN backing pages: %d
<3>[drm] nouveau %s: error pinning PRAMIN backing VRAM: %d
<7>[drm] nouveau %s: %s:%d - st=0x%0llx sz=0x%0llx
<7>[drm] nouveau %s: %s:%d - pramin=0x%llx, pte=%d, pte_end=%d
<7>[drm] nouveau %s: %s:%d - first vram page: 0x%08x
<3>[drm] nouveau %s: timeout: (0x100c80 & 1) == 0 (1)
<3>[drm] nouveau %s: 0x100c80 = 0x%08x
<3>[drm] nouveau %s: timeout: (0x100c80 & 1) == 0 (2)
<3>[drm] nouveau %s: PRAMIN flush timeout
/usr/src/packages/BUILD/kernel-desktop-2.6.34.10/linux-2.6.34/drivers/gpu/drm/nouveau/nouveau_drv.h <7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: no space while setting dither
<6>[drm] nouveau %s: Ch%d/0x%08x: 0x%08x
<6>[drm] nouveau %s: Ch%d/0x%08x: PUSH!
<7>[drm] nouveau %s: %s:%d - index %d
<3>[drm] nouveau %s: unknown depth %d
<7>[drm] nouveau %s: %s:%d - %s
<3>[drm] nouveau %s: no space while blanking crtc
<3>[drm] nouveau %s: no space while unblanking crtc
<3>[drm] nouveau %s: no space while committing crtc
<3>[drm] nouveau %s: No native mode, forcing panel scaling
<3>[drm] nouveau %s: timeout: DAC_DPMS_CTRL_PENDING(%d) == 0
<3>[drm] nouveau %s: DAC_DPMS_CTRL(%d) = 0x%08x
<7>[drm] nouveau %s: %s:%d - Using bios provided load_pattern of %d
<7>[drm] nouveau %s: %s:%d - Using default load_pattern of %d
<7>[drm] nouveau %s: %s:%d - Load was detected on output with or %d
<7>[drm] nouveau %s: %s:%d - Load was not detected on output with or %d
<7>[drm] nouveau %s: %s:%d - or %d mode %d
<7>[drm] nouveau %s: %s:%d - or %d
<3>[drm] nouveau %s: Encoder has no connector
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - Disconnecting DAC %d
<3>[drm] nouveau %s: no space while disconnecting DAC
<6>[drm] nouveau %s: Ch%d/0x%08x: 0x%08x
<3>[drm] nouveau %s: no space while connecting DAC
<6>[drm] nouveau %s: Detected a DAC output
<7>[drm] nouveau %s: %s:%d - or %d
<3>[drm] nouveau %s: Encoder has no connector
<3>[drm] nouveau %s: SOR-%d: no DP encoder table!
<7>[drm] nouveau %s: %s:%d - SOR-%d: running DP script 0
<3>[drm] nouveau %s: SOR-%d: link training failed
<7>[drm] nouveau %s: %s:%d - SOR-%d: running DP script 1
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s:%d - or %d mode %d
<3>[drm] nouveau %s: timeout: SOR_DPMS_CTRL_PENDING(%d) == 0
<3>[drm] nouveau %s: SOR_DPMS_CTRL(%d) = 0x%08x
<3>[drm] nouveau %s: timeout: SOR_DPMS_STATE_WAIT(%d) == 0
<3>[drm] nouveau %s: SOR_DPMS_STATE(%d) = 0x%08x
<3>[drm] nouveau %s: no space while connecting SOR
<6>[drm] nouveau %s: Ch%d/0x%08x: 0x%08x
<7>[drm] nouveau %s: %s:%d - Disconnecting SOR %d
<3>[drm] nouveau %s: no space while disconnecting SOR
<6>[drm] nouveau %s: Detected a TMDS output
<6>[drm] nouveau %s: Detected a LVDS output
<3>[drm] nouveau %s: Failed parsing LVDS table
<6>[drm] nouveau %s: Detected a DP output
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: no space while hiding cursor
<6>[drm] nouveau %s: Ch%d/0x%08x: 0x%08x
<6>[drm] nouveau %s: Ch%d/0x%08x: PUSH!
<3>[drm] nouveau %s: no space while unhiding cursor
<3>[drm] nouveau %s: timeout: CURSOR_CTRL2_STATUS == 0
<3>[drm] nouveau %s: CURSOR_CTRL2 = 0x%08x
<3>[drm] nouveau %s: Error allocating EVO channel memory: %d
<3>[drm] nouveau %s: Error initialising EVO PRAMIN heap: %d
<3>[drm] nouveau %s: Unable to allocate EVO RAMHT: %d
<3>[drm] nouveau %s: Error creating EVO DMA push buffer: %d
<3>[drm] nouveau %s: Error mapping EVO DMA push buffer: %d
<3>[drm] nouveau %s: Error mapping EVO control regs.
<7>[drm] nouveau %s: %s:%d - 0x610030: 0x%08x
<3>[drm] nouveau %s: unknown dac mode_ctrl: 0x%08x
<3>[drm] nouveau %s: unknown sor mode_ctrl: 0x%08x
<7>[drm] nouveau %s: %s:%d - type %d, or %d
<3>[drm] nouveau %s: unknown encoder!!
<3>[drm] nouveau %s: no DCB entry for %d %d
<6>[drm] nouveau %s: override script 0x%04x with 0x%04x for output LVDS-%d
<6>[drm] nouveau %s: override script 0x%04x with 0x%04x for output TMDS-%d
<3>[drm] nouveau %s: modeset on unsupported output type!
<7>[drm] nouveau %s: %s:%d - head %d pxclk: %dKHz
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: timeout: (0x610024 & 0x%08x) == 0x%08x
<3>[drm] nouveau %s: 0x610024 = 0x%08x
<3>[drm] nouveau %s: timeout: (0x610200 & 0x1e0000) == 0
<3>[drm] nouveau %s: 0x610200 = 0x%08x
<3>[drm] nouveau %s: timeout: SOR_DPMS_STATE_WAIT(%d) == 0
<3>[drm] nouveau %s: SOR_DPMS_STATE(%d) = 0x%08x
<7>[drm] nouveau %s: %s:%d - ram_amount %d
<3>[drm] nouveau %s: timeout: (0x6194e8 & 2) != 0
<3>[drm] nouveau %s: 0x6194e8 = 0x%08x
<3>[drm] nouveau %s: timeout: (0x610200 & 0x1e0000) != 0
<3>[drm] nouveau %s: timeout: (0x610200 & 0x40000000) == 0x40000000
<3>[drm] nouveau %s: timeout: CURSOR_CTRL2_STATUS == 0
<3>[drm] nouveau %s: CURSOR_CTRL2 = 0x%08x
<3>[drm] nouveau %s: timeout: CURSOR_CTRL2_STATUS_ACTIVE(%d)
<3>[drm] nouveau %s: CURSOR_CTRL2(%d) = 0x%08x
<3>[drm] nouveau %s: timeout: (0x610200 & 0x80000000) == 0
<3>[drm] nouveau %s: evo pushbuf stalled
<3>[drm] nouveau %s: Error creating EVO channel: %d
<4>[drm] nouveau %s: Off-chip encoder %d/%d unsupported
<4>[drm] nouveau %s: DCB encoder %d unknown
<7>[drm] nouveau %s: %s:%d - PDISPLAY_INTR_BH 0x%08x 0x%08x
<6>[drm] nouveau %s: %splugged %s
<7>[drm] nouveau %s: %s:%d - PDISPLAY_INTR 0x%08x 0x%08x
<3>[drm] nouveau %s: EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)
<3>[drm] nouveau %s: unknown PDISPLAY_INTR_0: 0x%08x
<3>[drm] nouveau %s: unknown PDISPLAY_INTR_1: 0x%08x
<7>[drm] nouveau %s: %s:%d -
<6>[drm] nouveau %s: Output %s is running on CRTC %d using output %c
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<6>[drm] nouveau %s: Load detected on head A
<7>[drm] nouveau %s: %s: reg %08x val %08x
<6>[drm] nouveau %s: Load detected on output %c
<6>[drm] nouveau %s: Setting dpms mode %d on vga encoder (output %d)
<7>[drm] nouveau %s: %s:%d -
<3>[drm] nouveau %s: Not restoring LVDS without native mode
<7>[drm] nouveau %s: %s:%d - Output mode on CRTC %d:
<7>[drm] nouveau %s: %s: reg %08x val %08x
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<6>[drm] nouveau %s: Output %s is running on CRTC %d using output %c
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<6>[drm] nouveau %s: Setting dpms mode %d on lvds encoder (output %d)
<3>[drm] nouveau %s: Not turning on LVDS without native mode
<6>[drm] nouveau %s: Setting dpms mode %d on tmds encoder (output %d)
<6>[drm] nouveau %s: Output %s is running on CRTC %d using output %c
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<6>[drm] nouveau %s: Setting dpms mode %d on TV encoder (output %d)
<6>[drm] nouveau %s: Probing TV encoders on I2C bus: %d
<7>[drm] nouveau %s: %s: reg %08x val %08x
<6>[drm] nouveau %s: No TV encoders found.
<6>[drm] nouveau %s: Detected TV encoder: %s
<4>[drm] nouveau %s: Invalid TV norm setting "%s"
<6>[drm] nouveau %s: Setting dpms mode %d on TV encoder (output %d)
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<6>[drm] nouveau %s: Load detected on output %c
<6>[drm] nouveau %s: Output %s is running on CRTC %d using output %c
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<7>[drm] nouveau %s: %s:%d - vpll: n1 %d n2 %d m1 %d m2 %d log2p %d
<7>[drm] nouveau %s: %s:%d - vpll: n %d m %d log2p %d
<7>[drm] nouveau %s: %s:%d -
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<7>[drm] nouveau %s: %s:%d - Setting dpms mode %d on CRTC %d
<7>[drm] nouveau %s: %s:%d - CTRC mode on CRTC %d:
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<7>[drm] nouveau %s: %s: reg %08x val %08x
<6>[drm] nouveau %s: Initial CRTC_OWNER is %d
<7>[drm] nouveau %s: %s:%d -
<4>[drm] nouveau %s: DCB type %d not known
<6>[drm] nouveau %s: Restoring CRTC_OWNER to %d.
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<7>[drm] nouveau %s: %s: head %d index 0x%02x data 0x%02x
<7>[drm] nouveau %s: %s: head %d reg %08x val %08x
<6>failed to evaluate _DSM: %d
<6>VGA switcheroo: detected DSM switching method %s handle
license=GPL and additional rights description=nVidia Riva/TNT/GeForce author=Stephane Marchesin parmtype=reg_debug:int parm=reg_debug:Register access debug bitmask:
0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,
0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,
0x100 vgaattr, 0x200 EVO (G80+). parmtype=tv_norm:charp parm=tv_norm:Default TV norm.
Supported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,
hd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.
Default: PAL
*NOTE* Ignored for cards with external TV encoders. parmtype=tv_disable:int parm=tv_disable:Disable TV-out detection
parmtype=override_conntype:int parm=override_conntype:Ignore DCB connector type parmtype=nofbaccel:int parm=nofbaccel:Disable fbcon acceleration parmtype=noaccel:int parm=noaccel:Disable all acceleration parmtype=ignorelid:int parm=ignorelid:Ignore ACPI lid status parmtype=uscript_tmds:int parm=uscript_tmds:TMDS output script table ID (>=GeForce 8) parmtype=uscript_lvds:int parm=uscript_lvds:LVDS output script table ID (>=GeForce 8) parmtype=duallink:int parm=duallink:Allow dual-link TMDS (>=GeForce 8) parmtype=vram_notify:int parm=vram_notify:Force DMA notifiers to be in VRAM parmtype=vram_pushbuf:int parm=vram_pushbuf:Force DMA push buffers to be in VRAM parmtype=vbios:charp parm=vbios:Override default VBIOS location parmtype=modeset:int parm=modeset:Enable kernel modesetting parmtype=noagp:int parm=noagp:Disable AGP parmtype=ctxfw:int parm=ctxfw:Use external firmware blob for grctx init (NV40) srcversion=7E624BC5E4B969EA5C68FFE alias=pci:v000012D2d*sv*sd*bc03sc*i* alias=pci:v000010DEd*sv*sd*bc03sc*i* depends=drm,drm_kms_helper,ttm,button,i2c-algo-bit vermagic=2.6.34.10-0.6-desktop SMP preempt mod_unload modversions 686 & 0 8 C U _ g q ~ nouveau nVidia Riva/TNT/GeForce 20090420 nouveau <3>[drm] nouveau %s: ntfy %d
%s unknown value 0x%08x %s (unknown bits 0x%08x) , nStatus:
read write PGRAPH_TRAP PGRAPH_TRAP_DISPATCH_FAULT PGRAPH_TRAP_DISPATCH_QUERY PGRAPH_TRAP_M2MF_NOTIFY PGRAPH_TRAP_M2MF_IN PGRAPH_TRAP_M2MF_OUT PGRAPH_TRAP_VFETCH_FAULT PGRAPH_TRAP_STRMOUT_FAULT PGRAPH_TRAP_CCACHE_FAULT PGRAPH_TRAP_UNKC04 PGRAPH_TRAP_TEXTURE PGRAPH_TRAP_MP PGRAPH_TRAP_TPDMA PGRAPH_NOTIFY PGRAPH_ERROR PGRAPH_COMPUTE_QUERY PGRAPH_ILLEGAL_MTHD PGRAPH_ILLEGAL_CLASS PGRAPH_DOUBLE_NOTIFY PGRAPH_BUFFER_NOTIFY PGRAPH_DATA_ERROR PGRAPH_SINGLE_STEP INVALID_VALUE INVALID_ENUM INVALID_OBJECT INVALID_BITFIELD MP_NO_REG_SPACE MP_BLOCK_SIZE_MISMATCH STACK_UNDERFLOW QUADON_ACTIVE TIMEOUT INVALID_OPCODE BREAKPOINT NOTIFICATION DATA_ERROR PROTECTION_ERROR RANGE_EXCEPTION LIMIT_COLOR LIMIT_ZETA ILLEGAL_MTHD DMA_R_PROTECTION DMA_W_PROTECTION FORMAT_EXCEPTION PATCH_EXCEPTION STATE_INVALID DOUBLE_NOTIFY NOTIFY_IN_USE METHOD_CNT BFR_NOTIFICATION DMA_VTX_PROTECTION DMA_WIDTH_A DMA_WIDTH_B STATE_IN_USE INVALID_STATE BAD_ARGUMENT PROTECTION_FAULT Sav Restor INIT_IO_RESTRICT_PROG DEV_REC &bios->lock INIT_REPEAT INIT_IO_RESTRICT_PLL INIT_END_REPEAT INIT_COPY INIT_NOT INIT_IO_FLAG_CONDITION INIT_INDEX_ADDRESS_LATCHED INIT_IO_RESTRICT_PLL2 INIT_PLL2 INIT_I2C_BYTE INIT_ZM_I2C_BYTE INIT_ZM_I2C INIT_TMDS INIT_ZM_TMDS_GROUP INIT_CR_INDEX_ADDRESS_LATCHED INIT_CR INIT_ZM_CR INIT_ZM_CR_GROUP INIT_CONDITION_TIME INIT_ZM_REG_SEQUENCE INIT_SUB_DIRECT INIT_COPY_NV_REG INIT_ZM_INDEX_IO INIT_COMPUTE_MEM INIT_RESET INIT_CONFIGURE_MEM INIT_CONFIGURE_CLK INIT_CONFIGURE_PREINIT INIT_IO INIT_SUB INIT_RAM_CONDITION INIT_NV_REG INIT_MACRO INIT_DONE INIT_RESUME INIT_TIME INIT_CONDITION INIT_IO_CONDITION INIT_INDEX_IO INIT_PLL INIT_ZM_REG INIT_RAM_RESTRICT_PLL INIT_8C INIT_8D INIT_GPIO INIT_COPY_ZM_REG INIT_RESERVED INIT_96 INIT_97 INIT_AUXCH INIT_ZM_AUXCH nouveau-%s-%d nouveaufb nouveau/nv%02x.ctxprog nouveau/nv%02x.ctxvals <3>[drm] nouveau %s: !!
blanked unblanked <3>[drm] nouveau %s: !!
<3>[drm] nouveau %s: !!
un PAL PAL-M PAL-N PAL-Nc NTSC-M NTSC-J hd480i hd480p hd576i hd576p hd720p hd1080i nv_backlight _DSM } 0 : 8& ' ) ( G B ' 0 a k 1 a J ` j w% Tr v7 Tr J Tr ` Tr j Tr r r U r S r r | (
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r_ {_ _ _ 4 _ ] h _ _ > A _ 0 _ ` ` ` (` # C` f` ` ` ` ` ` ` ` a a (a n O 5a ] prefetch nouveau_pci_remove nouveau_pci_probe driver NVReadVgaCrtc.clone.0 __func__.31210 NVWriteVgaCrtc.clone.1 __func__.31203 __func__.31111 nouveau_init nouveau_modeset nouveau_exit __mod_license434 __mod_description433 __mod_author432 __mod_reg_debugtype107 __param_reg_debug __param_str_reg_debug __mod_reg_debug105 __mod_tv_normtype100 __param_tv_norm __param_str_tv_norm __mod_tv_norm98 __mod_tv_disabletype92 __param_tv_disable __param_str_tv_disable __mod_tv_disable90 __mod_override_conntypetype88 __param_override_conntype __param_str_override_conntype __mod_override_conntype86 __mod_nofbacceltype84 __param_nofbaccel __param_str_nofbaccel __mod_nofbaccel82 __mod_noacceltype80 __param_noaccel __param_str_noaccel __mod_noaccel78 __mod_ignorelidtype76 __param_ignorelid __param_str_ignorelid __mod_ignorelid74 __mod_uscript_tmdstype72 __param_uscript_tmds __param_str_uscript_tmds __mod_uscript_tmds70 __mod_uscript_lvdstype68 __param_uscript_lvds __param_str_uscript_lvds __mod_uscript_lvds66 __mod_duallinktype64 __param_duallink __param_str_duallink __mod_duallink62 __mod_vram_notifytype60 __param_vram_notify __param_str_vram_notify __mod_vram_notify58 __mod_vram_pushbuftype56 __param_vram_pushbuf __param_str_vram_pushbuf __mod_vram_pushbuf54 __mod_vbiostype52 __param_vbios __param_str_vbios __mod_vbios50 __mod_modesettype48 __param_modeset __param_str_modeset __mod_modeset46 __mod_noagptype44 __param_noagp __param_str_noagp __mod_noagp42 __mod_ctxfwtype40 __param_ctxfw __param_str_ctxfw __mod_ctxfw38 pciidlist nouveau_stub_takedown nouveau_init_engine_ptrs nouveau_card_takedown __func__.31074 nouveau_card_init_channel nouveau_switcheroo_can_switch nouveau_switcheroo_set_state nouveau_vga_set_decode __func__.31054 __func__.31092 nouveau_channel_pushbuf_ctxdma_init __func__.30667 __func__.30657 nouveau_ioctl_fifo_alloc nouveau_ioctl_fifo_free __func__.30682 nv_rd32 nouveau_mem_detect_nforce nv10_mem_set_region_tiling split_block CSWTCH.32 nouveau_ramht_hash_handle __func__.30579 nouveau_gpuobj_instance_get kzalloc.clone.0 nouveau_ramht_entry_valid nouveau_ramht_insert __func__.30601 nouveau_ramht_remove __func__.30614 __func__.30639 __func__.30672 __func__.30658 __func__.30650 __func__.30630 __func__.30695 __func__.30701 nouveau_gpuobj_channel_init_pramin __func__.30810 __func__.30739 __func__.30645 __func__.30761 __func__.30790 __func__.30823 __func__.30841 nouveau_call_method nouveau_pgraph_intr_swmthd nouveau_print_enum_names_ nouveau_print_bitfield_names_ nouveau_graph_dump_trap_info nsource_names nstatus_names nstatus_names_nv10 nv_wr32 nouveau_ratelimit __func__.30995 nouveau_ratelimit_state nv50_pgraph_mp_trap nv50_mp_exec_error_names nv50_pfb_vm_trap nv50_pgraph_tp_trap nouveau_graph_trapped_channel nouveau_graph_trap_info nouveau_fifo_swmthd nv50_pgraph_trap_handler nouveau_pgraph_irq_handler __func__.31009 nv50_pgraph_irq_handler nv50_data_error_names nouveau_fifo_irq_handler nouveau_notifier_gpuobj_dtor __func__.30587 nouveau_sgdma_destroy __func__.30648 nouveau_sgdma_populate __func__.30586 nouveau_sgdma_clear __func__.30595 nouveau_sgdma_unbind __func__.30636 nouveau_sgdma_bind __func__.30616 nouveau_sgdma_backend OUT_RING nv50_dma_wait nouveau_bo_fixup_align nouveau_bo_invalidate_caches nouveau_bo_verify_access nouveau_bo_init_mem_type nouveau_bo_create_ttm_backend_entry nouveau_bo_del_ttm __func__.30632 nouveau_bo_evict_flags nouveau_bo_move_m2mf nouveau_bo_move_flipd nouveau_bo_move_flips nouveau_bo_move nouveau_fence_del validate_list validate_fini_list validate_fini validate_init __func__.30727 nouveau_gem_pushbuf_validate nouveau_gem_pushbuf_reloc_apply nouveau_ttm_mem_global_release nouveau_ttm_mem_global_init __func__.30588 nv_two_heads powerctrl_1_shift nouveau_hw_decode_pll NVWritePRMVIO __func__.30766 setPLL_double_lowregs __func__.30640 __func__.30646 setPLL_double_highregs __func__.30703 __func__.30710 nv_save_state_ext __func__.30732 __func__.30689 setPLL_single nv_load_state_ext __func__.30696 __func__.30758 nv_load_state_vga __func__.30782 nv_save_state_vga __func__.30789 nv_load_state_ramdac nouveau_hw_fix_bad_vpll nv_save_state_ramdac getMNP_single getMNP_double nv10_calc_arb nv04_update_arb __func__.30664 __func__.30676 init_end_repeat init_done init_8c init_8d init_reserved clkcmptable parse_bit_M_tbl_entry parse_bit_displayport_tbl_entry findstr parse_dcb30_gpio_entry parse_dcb40_gpio_entry divine_connector_type fixup_legacy_connector score_vbios parse_bit_table parse_bit_structure parse_bit_i_tbl_entry parse_bit_C_tbl_entry parse_bit_display_tbl_entry parse_bit_init_tbl_entry parse_bit_lvds_tbl_entry parse_bit_tmds_tbl_entry parse_bit_U_tbl_entry parse_bit_A_tbl_entry parse_bmp_structure nouveau_parse_vbios_struct parse_dcb20_entry read_dcb_i2c_entry merge_like_dcb_entries parse_dcb_gpio_table parse_dcb_connector_table valid_reg parse_init_table itbl_entry parse_init_tables valid_idx_port init_resume init_sub init_sub_direct init_not init_repeat new_dcb_entry fabricate_vga_output parse_dcb15_entry fabricate_tv_output parse_lvds_manufacturer_table_header NVShadowVBIOS nv04_methods nv50_methods load_vbios_pci parse_dcb_table munge_reg init_time bios_rd32 bios_condition_met init_condition init_condition_time init_ram_condition bios_wr32 init_97 init_96 init_zm_reg_group_addr_latched init_copy_zm_reg init_ram_restrict_zm_reg_group init_zm_reg init_macro init_nv_reg init_compute_mem init_copy_nv_reg init_zm_reg_sequence init_idx_addr_latched init_gpio bios_idxprt_wr init_configure_preinit init_zm_index_io init_zm_cr init_zm_cr_group init_reset load_nv17_hwsq_ucode_entry.clone.0 init_io load_vbios_pramin load_vbios_prom run_digital_op_script run_lvds_table dcb_entry_idx_from_crtchead get_tmds_index_reg init_zm_tmds_group init_tmds init_i2c_device_find init_zm_auxch init_auxch init_zm_i2c init_zm_i2c_byte init_i2c_byte bios_idxprt_rd init_io_condition io_flag_condition_met init_io_flag_condition init_io_restrict_prog init_index_io init_configure_mem init_cr init_cr_idx_adr_latch init_copy get_fp_strap parse_fp_mode_table nv50_pll_set setPLL init_ram_restrict_pll init_pll init_configure_clk init_pll2 init_io_restrict_pll2 init_io_restrict_pll __key.32388 nv50_i2c_setscl nv4e_i2c_setscl nv04_i2c_getscl nv4e_i2c_setsda nv50_i2c_getscl nv50_i2c_getsda nv4e_i2c_getscl nv4e_i2c_getsda nv50_i2c_setsda nv04_i2c_setsda nv04_i2c_setscl nv04_i2c_getsda nv50_i2c_port nouveau_user_framebuffer_create_handle nouveau_user_framebuffer_destroy nouveau_framebuffer_funcs nouveau_user_framebuffer_create nouveau_connector_best_encoder nouveau_connector_mode_valid find_encoder_by_type nouveau_connector_set_encoder nouveau_connector_force nouveau_connector_destroy __func__.31391 nouveau_connector_set_property nouveau_connector_native_mode __func__.31480 nouveau_connector_get_modes scaler_modes nouveau_connector_ddc_prepare __func__.31246 __func__.31239 __func__.31147 nouveau_connector_ddc_finish nouveau_connector_ddc_detect nouveau_connector_detect nouveau_connector_create_lvds nouveau_connector_funcs nouveau_connector_helper_funcs __func__.31575 nouveau_fbcon_gamma_set nouveau_fbcon_gamma_get nouveau_fbcon_has_vesafb_or_efifb nouveau_fbcon_create nouveau_fbcon_helper_funcs nouveau_fbcon_ops __warned.30300 nv04_fbcon_ops nv50_fbcon_ops __func__.31846 nouveau_fbcon_sync nouveau_dp_max_voltage_swing nouveau_dp_max_pre_emphasis __func__.30867 auxch_rd __func__.30851 nouveau_dp_link_train_adjust __func__.30779 auxch_wr nouveau_dp_link_train_commit __func__.30802 nouveau_dp_link_train_set __func__.30828 nv04_fifo_init_reset nv04_fifo_do_load_context nv10_fifo_init_reset nv10_fifo_do_load_context nv40_fifo_init_reset nv40_fifo_do_load_context nv40_fifo_init_ramxx nv50_fifo_init_thingo __func__.30582 nv50_fifo_channel_disable __func__.30602 nv50_fifo_channel_enable __func__.30594 __func__.30635 __func__.30628 __func__.30624 __func__.30617 __func__.30611 __func__.30607 __func__.30642 __func__.30654 __func__.30665 __func__.30675 __func__.30691 nv04_graph_mthd_set_ref nv04_graph_mthd_set_operation nv04_graph_ctx_regs nv04_graph_mthds_set_operation nv04_graph_mthds_sw nv17_graph_ctx_regs_find_offset nv17_graph_ctx_regs nv10_graph_ctx_regs_find_offset nv10_graph_ctx_regs nv10_graph_create_pipe nv10_graph_load_pipe nv10_graph_save_pipe nv17_graph_mthd_lma_enable nv17_graph_mthd_lma_window __func__.30884 nv17_graph_celsius_mthds nv25_graph_context_init nv20_graph_context_init nv2a_graph_context_init nv30_31_graph_context_init nv35_36_graph_context_init nv34_graph_context_init nv40_graph_transfer_context nv50_graph_nvsw_vblsem_release_val nv50_graph_nvsw_vblsem_offset nv50_graph_nvsw_dma_vblsem nv50_graph_init_regs__nv __func__.30598 nv50_graph_do_load_context nv50_graph_init_ctxctl __func__.30610 nv50_graph_nvsw_vblsem_release __func__.30621 __func__.30591 __func__.30605 __func__.30625 __func__.30651 __func__.30660 __func__.30673 nv50_graph_nvsw_methods nv40_graph_construct_shader CSWTCH.25 nv40_graph_construct_general nv40_graph_construct_state3d nv40_graph_construct_state3d_2 gr_def xf_emit nv50_graph_construct_gene_unk9 nv50_graph_construct_gene_unk1 nv50_graph_construct_gene_unk5 nv50_graph_construct_gene_unk6 nv50_graph_construct_gene_ropc nv50_graph_construct_xfer_tp_x5 nv50_graph_construct_xfer_tp_x4 cp_ctx nv50_graph_construct_mmio nv50_graph_construct_xfer_tp2 nv50_graph_construct_xfer2 nv50_graph_construct_gene_m2mf nv50_graph_construct_gene_unk10 nv50_graph_construct_gene_unk8 nv50_graph_construct_xfer_tp_x1 nv50_graph_construct_gene_unk2 nv50_graph_construct_gene_unk3 nv50_graph_construct_gene_unk4 nv50_graph_construct_gene_unk7 nv50_graph_construct_xfer_tp_x3 nv50_graph_construct_xfer_tp_x2 nv50_graph_construct_xfer_tp nv50_graph_construct_xfer1 nv04_instmem_configure_fixed_tables __func__.30596 __func__.30652 __func__.30705 nv50_crtc_dpms nv50_crtc_mode_fixup nv50_crtc_restore nv50_crtc_save nv50_crtc_lut_load __warned.29476 __func__.31441 nv50_crtc_gamma_set nv50_crtc_destroy __func__.31520 nv50_crtc_set_dither __func__.31464 nv50_crtc_do_mode_set_base __func__.31632 nv50_crtc_mode_set_base __func__.31454 nv50_crtc_commit __func__.31604 nv50_crtc_prepare __func__.31576 nv50_crtc_mode_set __func__.31664 nv50_crtc_set_scale __func__.31494 nv50_crtc_funcs nv50_crtc_helper_funcs __func__.31679 nv50_dac_prepare nv50_dac_commit nv50_dac_restore nv50_dac_save nv50_dac_detect __func__.31166 nv50_dac_dpms __func__.31179 nv50_dac_mode_fixup __func__.31198 nv50_dac_destroy __func__.31225 nv50_dac_disconnect __func__.31153 nv50_dac_mode_set __func__.31219 nv50_dac_encoder_funcs nv50_dac_helper_funcs __func__.31233 nv50_sor_prepare nv50_sor_commit nv50_sor_restore nv50_sor_save nv50_sor_mode_fixup __func__.31194 nv50_sor_dp_link_train __func__.31161 nv50_sor_destroy __func__.31224 nv50_sor_dpms nv50_sor_disconnect __func__.31171 nv50_sor_mode_set __func__.31214 nv50_sor_encoder_funcs nv50_sor_helper_funcs __func__.31235 nv50_cursor_set_offset __func__.30751 nv50_cursor_set_pos nv50_cursor_hide __func__.30740 nv50_cursor_show __func__.30731 __func__.30760 nv50_display_vblank_crtc_handler nv50_evo_channel_del nv50_evo_dmaobj_new.clone.0 nv50_evo_channel_new nv50_display_irq_head __func__.31311 nv50_display_script_select nv50_display_unk20_handler __func__.31401 nv50_display_disable __func__.31238 __func__.31196 __func__.31290 __func__.31267 __func__.31420 nv04_dac_mode_fixup nv04_dac_destroy __func__.31489 sample_load_twice nv04_dac_commit nv04_dac_prepare nv04_dac_save __func__.31204 nv04_dac_detect __func__.31240 __func__.31211 nv04_dac_restore nv04_dac_mode_set __func__.31141 nv17_dac_detect nv04_dac_dpms nv04_dac_helper_funcs nv04_dac_funcs nv17_dac_helper_funcs nv04_dfp_prepare_sel_clk nv04_dfp_destroy __func__.31490 nv04_dfp_mode_fixup nv04_dfp_restore nv04_dfp_mode_set __func__.31428 __func__.31177 nv04_dfp_prepare nv04_dfp_commit nv04_dfp_save nv04_lvds_dpms nv04_tmds_dpms nv04_tmds_helper_funcs nv04_dfp_funcs nv04_lvds_helper_funcs nv04_tv_mode_set nv04_tv_destroy nv04_tv_commit nv04_tv_bind __func__.31015 __func__.31037 nv04_tv_prepare nv04_tv_dpms __func__.31044 nv04_tv_encoder_info __func__.30945 __compound_literal.0 nv17_tv_mode_fixup nv17_tv_mode_set nv17_tv_set_property nv17_tv_create_resources nv17_tv_get_modes modes nv17_tv_mode_valid nv17_tv_dpms nv17_tv_destroy __func__.31652 nv17_tv_save nv17_tv_restore nv17_tv_prepare nv42_tv_sample_load nv17_tv_detect nv17_tv_commit nv17_tv_funcs nv17_tv_helper_funcs nv17_tv_slave_funcs tv_setup_filter fparams tv_save_filter tv_load_filter __func__.31101 nv_crtc_mode_fixup nv04_crtc_cursor_move nv_crtc_gamma_load nv_crtc_gamma_set nv_crtc_calc_state_ext __func__.31397 nv04_crtc_cursor_set nv_crtc_destroy __func__.31526 nv_crtc_mode_set_vga nv_crtc_restore nv_crtc_save nv_crtc_prepare __func__.31217 crtc_wr_cio_state nv04_crtc_mode_set_base nv_crtc_commit nv_crtc_mode_set_regs nv_crtc_dpms __func__.31253 __func__.31407 nv_crtc_mode_set nv04_crtc_funcs nv04_crtc_helper_funcs nv04_display_store_initial_head_owner __func__.30948 __func__.30849 __func__.30941 __func__.31302 __func__.31340 nv04_cursor_set_pos __func__.30788 nv04_cursor_hide __func__.30781 nv04_cursor_set_offset nv04_cursor_show nv04_fbcon_grobj_new nv50_set_intensity nv40_set_intensity nv40_get_intensity nv50_get_intensity nv40_bl_ops nv50_bl_ops nouveau_dsm_init nouveau_dsm_get_client_id nouveau_dsm_priv nouveau_dsm nouveau_dsm_muid nouveau_dsm_power_state nouveau_dsm_switchto nouveau_dsm_detect nouveau_dsm_handler __mod_srcversion257 __mod_alias255 __mod_alias254 __module_depends ____versions __mod_vermagic5 nouveau_gpuobj_channel_takedown ttm_bo_mmap unregister_framebuffer nouveau_i2c_fini drm_framebuffer_cleanup nouveau_bo_pin nv40_fb_init strcpy pci_save_state nv50_fifo_destroy_context drm_open nouveau_ignorelid drm_fasync drm_mode_vrefresh nouveau_hw_get_clock ioread32 dma_ops drm_helper_initial_config nv20_graph_takedown __udelay nouveau_ttm_mmap drm_i2c_encoder_init drm_poll nv50_fifo_takedown nouveau_bo_new release_firmware nouveau_pci_suspend ttm_bo_global_release drm_mode_object_find drm_mode_crtc_set_gamma_size ttm_bo_clean_mm nouveau_calc_arb dev_get_drvdata drm_get_resource_len nv50_fifo_load_context nouveau_sgdma_init_ttm drm_fb_helper_fill_fix backlight_device_unregister nv40_graph_destroy_context _copy_from_user pci_enable_device nv04_cursor_init nv20_graph_set_region_tiling nouveau_fence_handler iowrite32 nv50_fifo_init nv10_graph_channel drm_framebuffer_init drm_core_get_reg_ofs drm_agp_info nouveau_ioctl_gpuobj_free nouveau_notifier_init_channel nouveau_channel_alloc nv50_grctx_init nouveau_irq_preinstall drm_fb_helper_setcmap nv10_graph_context_switch __this_module nv50_mem_vm_bind_linear nouveau_sgdma_takedown nv20_graph_grclass nv04_graph_unload_context snprintf nv04_fb_takedown nouveau_card_init nouveau_irq_handler drm_mode_probed_add ttm_bo_global_init nouveau_tv_norm drm_agp_enable nouveau_gem_object_del i2c_bit_add_bus nv10_fb_set_region_tiling cfb_copyarea nv04_graph_load_context nouveau_bios_parse_lvds_table ttm_global_item_unref nv50_graph_fifo_access nv04_tv_identify nv17_tv_state_load drm_mm_put_block drm_gem_object_handle_free ioread16 OUT_RINGp nv04_fifo_init request_firmware nouveau_bo_map nouveau_fbcon_zfill i2c_dp_aux_add_bus nv40_graph_load_context nv04_graph_takedown nouveau_gpuobj_gart_dma_new nv50_display_init nv04_instmem_bind nouveau_backlight_exit ttm_bo_move_ttm nouveau_sgdma_init ttm_bo_wait_unreserved NVBlankScreen vga_switcheroo_register_client nv50_fb_takedown nv10_graph_load_context nouveau_reg_debug mtrr_del iounmap kref_get nv50_cursor_init nv50_crtc_cursor_move cleanup_module dma_supported memcpy nv04_fifo_destroy_context nv50_display_irq_handler kfree nv17_gpio_set drm_mode_config_init kref_init nouveau_hw_save_vga_fonts nouveau_gpuobj_suspend_cleanup nv04_fb_init nv20_graph_load_context nouveau_sgdma_get_page nouveau_notifier_offset nv17_tv_norms drm_crtc_cleanup iowrite16 nouveau_vbios ttm_global_item_ref ttm_bo_device_release nouveau_gem_ioctl_cpu_prep nouveau_gpuobj_new framebuffer_alloc nouveau_fbcon_gpu_lockup vga_switcheroo_unregister_handler pci_set_power_state drm_encoder_cleanup nv17_tv_update_properties nouveau_override_conntype param_set_charp nouveau_fbpercrtc nv17_dac_sample_load nouveau_grctx_prog_load _raw_spin_lock_irqsave nv50_display_irq_hotplug_bh drm_crtc_init NVSetOwner nv50_graph_context_switch _raw_spin_lock nv04_instmem_populate nv50_fb_init nouveau_bios_init nv04_fifo_channel_id init_module nouveau_gem_ioctl_new nouveau_bios_gpio_entry nouveau_ioctl_setparam nv50_instmem_finish_access nouveau_gpuobj_del nv17_tv_create nouveau_bo_rd16 drm_gem_object_lookup nouveau_ioctls nv50_crtc_cursor_set nv04_fbcon_accel_init acquire_console_sem drm_mode_debug_printmodeline acpi_get_name release_console_sem nouveau_bo_unmap drm_sysfs_connector_add drm_crtc_helper_set_mode nouveau_gpuobj_channel_init nouveau_bo_driver nouveau_hw_get_pllvals drm_irq_uninstall _raw_spin_lock_irq drm_gem_object_alloc vga_switcheroo_client_fb_set ttm_bo_kunmap nouveau_fence_flush iowrite8 ___ratelimit schedule_timeout drm_fb_helper_blank drm_fb_helper_check_var nouveau_uscript_tmds nouveau_fence_unref nv04_instmem_unbind drm_fb_helper_add_connector drm_fb_helper_setcolreg nouveau_irq_postinstall pci_bus_read_config_dword drm_connector_property_set_value nouveau_fbcon_probe screen_info drm_unbind_agp pci_enable_rom nouveau_bo_unpin ttm_agp_backend_init nouveau_grctx_vals_load drm_mode_create_scaling_mode_property nv50_sor_create drm_get_dev nv04_display_destroy nv10_fifo_destroy_context ioremap_nocache nv04_graph_destroy_context nouveau_mem_release nouveau_fence_channel nv04_fbcon_imageblit nv50_instmem_takedown nv04_graph_channel nouveau_noagp nouveau_gpuobj_resume nouveau_bios_takedown __free_pages nouveau_firstopen nv40_fifo_init nv30_graph_init nouveau_gpuobj_new_fake drm_ioctl nouveau_hw_setpll i2c_del_adapter nv40_fifo_unload_context nv50_graph_destroy_context drm_helper_crtc_in_use nouveau_gpuobj_late_takedown nv04_dfp_update_fp_control nv20_graph_init nouveau_channel_owner nouveau_run_vbios_init nv04_graph_context_switch drm_exit drm_gem_object_free nouveau_load nv50_display_create acpi_get_handle ttm_bo_mem_space drm_debug nv04_timer_init pci_find_capability call_lvds_script nv50_instmem_populate nouveau_gem_ioctl_info nv10_fifo_create_context nv40_graph_create_context nv50_graph_takedown drm_mode_connector_update_edid_property nv50_display_destroy nouveau_mem_takedown drm_core_get_map_ofs nouveau_gpuobj_init drm_connector_init nv40_fifo_destroy_context nv10_fifo_unload_context __mod_pci_device_table NVReadVgaGr nv50_fbcon_accel_init nouveau_mem_init unlock_page nv40_graph_channel nv10_fifo_load_context nv04_instmem_clear __create_workqueue_key preempt_schedule drm_sysfs_connector_remove ttm_bo_device_init nouveau_hw_load_state_palette ttm_bo_wait nv50_crtc_create ttm_bo_init_mm nouveau_bios_fp_mode ttm_bo_wait_cpu nouveau_duallink nouveau_encoder_connector_get drm_add_edid_modes nv10_graph_init nv50_fifo_unload_context nouveau_gpuobj_sw_new ttm_tt_bind nv04_fifo_disable nouveau_ioctl_getparam nouveau_dp_link_train nv04_fifo_reassign drm_init nv40_graph_set_region_tiling nv04_dac_output_offset nouveau_lastclose nouveau_dma_init nouveau_gpuobj_suspend pci_get_domain_bus_and_slot nv40_fb_set_region_tiling vga_client_register get_pll_limits nouveau_dp_auxch nouveau_ttm_global_init mutex_lock nv50_instmem_bind warn_slowpath_null nouveau_channel_cleanup nv50_fifo_create_context nv04_fbcon_fillrect nouveau_backlight_init nv04_timer_read _raw_spin_unlock_irq nouveau_dma_wait nouveau_pci_resume drm_fb_helper_single_fb_probe nv10_graph_takedown nouveau_ioctl_grobj_alloc ttm_bo_evict_mm copy_to_user strncpy nouveau_notifier_takedown_channel strcasecmp ttm_bo_unreserve nv04_instmem_resume NVReadVgaSeq nv04_dfp_bind_head drm_fb_helper_fill_var nouveau_ctxfw nv50_instmem_prepare_access nv04_crtc_create ttm_bo_kmap nv17_tv_update_rescaler drm_free_agp nouveau_gpuobj_dma_new nouveau_dp_i2c_aux_ch pci_map_rom drm_helper_encoder_in_use nouveau_gem_ioctl_cpu_fini nv04_fifo_create_context nv04_mc_init drm_gem_handle_create nouveau_gpuobj_ref_find nv04_tv_create nv04_fbcon_copyarea drm_put_dev nv10_graph_unload_context nv40_graph_init nouveau_unregister_dsm_handler nouveau_mode_config_funcs drm_mode_create_tv_properties nv50_gpio_get drm_mode_duplicate nv10_mem_set_tiling printk nv40_grctx_init __mutex_init drm_helper_mode_fill_fb_struct nv04_dac_create nouveau_fence_emit nouveau_bios_run_init_table drm_mode_set_name drm_mode_create_dvi_i_properties current_task nouveau_gpuobj_new_ref _raw_spin_unlock_irqrestore nv04_display_restore cfb_imageblit nouveau_bo_placement_set nouveau_hw_load_state nv50_fbcon_copyarea pci_restore_state NVWriteVgaGr acpi_lid_open kmem_cache_alloc_notrace ioread8 nouveau_bios_embedded_edid nouveau_mem_alloc_block nv04_dfp_disable nv04_instmem_takedown NVWriteVgaSeq nv40_graph_takedown ttm_bo_unref nv04_dfp_get_bound_head nv04_fifo_unload_context drm_irq_install drm_mode_connector_attach_encoder ttm_mem_global_release memset nouveau_gpuobj_early_init nv04_fifo_load_context nv50_graph_unload_context nv04_graph_init drm_helper_connector_dpms nv04_timer_takedown pci_set_master nv40_mc_init drm_get_resource_start nv40_fb_takedown nouveau_wait_for_idle param_get_charp nv17_ctv_update_rescaler ttm_mem_global_init nv10_fb_takedown drm_fb_helper_pan_display nv04_fifo_enable ttm_bo_synccpu_write_grab nouveau_gpuobj_ref_add drm_connector_attach_property nv17_tv_modes fb_set_suspend nouveau_irq_uninstall nv10_graph_destroy_context nv50_mc_init nouveau_uscript_lvds strcmp nouveau_mem_free_block nv50_graph_channel nouveau_fence_fini drm_connector_cleanup jiffies nouveau_gpuobj_gr_new nv50_graph_create_context nv17_tv_state_save nouveau_fence_init nv40_fifo_create_context sprintf nouveau_vram_pushbuf nv10_mem_expire_tiling nv50_cursor_fini nv10_fifo_channel_id nv04_instmem_finish_access nouveau_dp_detect nv40_graph_unload_context nouveau_framebuffer_create drm_encoder_init param_set_int drm_vblank_init nv04_fifo_cache_pull vfree nouveau_ioctl_notifier_alloc drm_fb_helper_init_crtc_count nv50_instmem_clear nv40_graph_grclass nv30_graph_grclass mutex_unlock cfb_fillrect nv50_fbcon_fillrect nouveau_gpuobj_takedown __const_udelay nouveau_bios_dp_table acpi_evaluate_object nv50_dma_push nouveau_fence_signalled queue_work ttm_bo_reserve nouveau_gpuobj_ref_del pci_get_class nv20_graph_create_context nouveau_hw_save_state nv10_graph_create_context nv10_graph_set_region_tiling drm_helper_probe_single_connector_modes nouveau_crtc_connector_get nv40_fifo_load_context __tracepoint_kmalloc nv50_fbcon_imageblit nouveau_hw_pllvals_to_clk drm_get_connector_name nouveau_calc_pll_mnp nv04_dfp_create drm_gem_object_free_unlocked drm_mmap nv50_graph_load_context nv20_graph_unload_context nouveau_gem_object_new backlight_device_register drm_order drm_cvt_mode mtrr_add nouveau_mem_detect usecs_to_jiffies nv04_dac_update_dacclk ttm_bo_synccpu_write_release vga_switcheroo_register_handler nv50_mem_vm_unbind nv20_graph_destroy_context nouveau_i2c_init ttm_bo_init nouveau_fence_new i2c_transfer nouveau_bios_run_display_table nv50_crtc_set_clock nouveau_unload nouveau_fence_update ttm_bo_validate pci_disable_device nv50_mc_takedown drm_fb_helper_free nouveau_i2c_find malloc_sizes drm_mode_destroy nouveau_noaccel nouveau_preclose nv17_gpio_get dma_set_mask nv04_mc_takedown ttm_bo_move_accel_cleanup nouveau_max_ioctl nv40_mc_takedown nv50_gpio_set nouveau_gem_new pci_disable_rom nouveau_gem_ioctl_pushbuf nouveau_bo_wr16 slab_buffer_size nv04_graph_fifo_access nv50_instmem_init drm_mode_config_cleanup nouveau_wait_until dev_set_drvdata pci_unmap_rom page_address nv50_instmem_unbind nouveau_bo_rd32 framebuffer_release nouveau_grctx_fini nouveau_vram_notify nv50_instmem_suspend nv50_fifo_channel_id nv50_display_irq_handler_bh nv04_display_create param_get_int nouveau_register_dsm_handler nv50_instmem_resume ttm_bo_move_memcpy nv04_fifo_cache_flush nv10_graph_grclass vmalloc _raw_spin_unlock nouveau_dma_pre_init nouveau_bios_connector_entry drm_get_edid nouveau_bo_wr32 nv50_crtc_blank run_tmds_table nouveau_connector_create drm_helper_resume_force_mode nv04_instmem_suspend nv10_fifo_init nouveau_channel_free nv50_graph_init nouveau_mem_init_agp nouveau_fbcon_remove drm_crtc_helper_set_config nv17_tv_norm_names drm_mode_remove nv04_graph_grclass kref_put nouveau_fence_wait msleep nouveau_mem_init_heap nv50_dac_create nv50_graph_grclass nouveau_mem_close nv04_instmem_init nouveau_fence_ref nv04_graph_create_context __kmalloc nouveau_ttm_global_release drm_mode_create_dithering_property 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