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<3>%s %s: Frequency greater than maxclock (%ld kHz)
<7>%s %s: desired pixclock: %ld kHz
<6>%s %s: virtual resolution set to maximum of %dx%d
<3>%s %s: mode %dx%dx%d rejected... virtual resolution too high to fit into video memory!
<3>%s %s: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)
<7>%s %s: Unsupported bpp size: %d
<7>%s %s: Framebuffer unregistered
<3>%s %s: could not register fb device; err = %d!
<7>%s %s: (RAM start set to: 0x%p)
<7>%s %s: wrong initial video mode
<7>%s %s: choking on default var... umm, no good.
<3>cirrusfb: Cannot enable PCI device
<3>cirrusfb: could not allocate memory
<4>%s %s: Unknown memory size!
<3>%s %s: cannot reserve region 0x%lx, abort
<6>%s %s: Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx
<7>%s %s: Found PCI device, base address 0 is 0x%Lx, btype set to %d
<7>%s %s: base address 1 is 0x%Lx
<7>%s %s: Attempt to get PCI info for Cirrus Graphics Card
<7>%s %s: Board address: 0x%lx, register address: 0x%lx
<7>%s %s: Read MCLK of %ld kHz
<7>%s %s: Using VCLK = MCLK/2
<7>%s %s: Set %s as pixclock source.
<7>%s %s: ENTER, blank mode = %d
<3>%s %s: Warning: Unknown board type
<3>%s %s: What's this? requested color depth == %d.
<7>%s %s: Requested mode: %dx%dx%d
<7>%s %s: VCLK freq: %ld kHz nom: %d den: %d div: %d
<7>%s %s: preparing for 1 bit deep display
<7>%s %s: preparing for 8 bit deep display
<7>%s %s: preparing for 16 bit deep display
<7>%s %s: preparing for 24 bit deep display
Board address: 0x%lx, register address: 0x%lx
Attempt to get PCI info for Cirrus Graphics Card
Found PCI device, base address 0 is 0x%Lx, btype set to %d
choking on default var... umm, no good.
preparing for 24 bit deep display
preparing for 16 bit deep display
preparing for 8 bit deep display
preparing for 1 bit deep display
VCLK freq: %ld kHz nom: %d den: %d div: %d
nom != NULL den != NULL div != NULL cinfo->btype != BT_NONE pdev != NULL *display != 0 cirrusfb <7>%s %s: Using VCLK = MCLK
MCLK/2 MCLK cinfo != NULL <7>%s %s: EXIT, returning 0
<7>%s %s: EXIT, returning 1
info->screen_size > 0 <4>%s %s: unknown Board
<4>%s %s: unknown board
<7>%s %s: CRT0: %d
<7>%s %s: CRT1: %d
<7>%s %s: CRT2: %d
<7>%s %s: CRT3: 128+%d
<7>%s %s: CRT4: %d
<7>%s %s: CRT5: %d
<7>%s %s: CRT6: %d
<7>%s %s: CRT7: %d
<7>%s %s: CRT9: %d
<7>%s %s: CRT10: %d
<7>%s %s: CRT11: 64+32+%d
<7>%s %s: CRT12: %d
<7>%s %s: CRT15: %d
<7>%s %s: CRT16: %d
<7>%s %s: CRT18: 0xff
<7>%s %s: CRT1a: %d
<7>%s %s: CRT1e: %d
<7>%s %s: CL_SEQR1: %d
640x480@60 Framebuffer unregistered
base address 1 is 0x%Lx
wrong initial video mode
(RAM start set to: 0x%p)
CL SD64 CL Piccolo CL Picasso CL Spectrum CL Picasso4 CL Alpine CL GD5480 CL Laguna CL Laguna AGP EXIT, returning 0
EXIT, returning 1
ENTER, blank mode = %d
CL_SEQR1: %d
CRT1e: %d
CRT1a: %d
CRT18: 0xff
CRT16: %d
CRT15: %d
CRT12: %d
CRT11: 64+32+%d
CRT10: %d
CRT9: %d
CRT7: %d
CRT6: %d
CRT5: %d
CRT4: %d
CRT3: 128+%d
CRT2: %d
CRT1: %d
CRT0: %d
Requested mode: %dx%dx%d
Using VCLK = MCLK/2
Using VCLK = MCLK
Read MCLK of %ld kHz
Set %s as pixclock source.
Unsupported bpp size: %d
desired pixclock: %ld kHz
P 0 0 : 0 I 3 : `: 8: `: : : : 9 9 = A xA A xA A A A 0A 0A get_pci_addrs cirrusfb_register M M _ _ _ _ _ " _ _ _ _ _ ! " * _ _ _ _ _ " 6 M M B M M P To L @
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uUHhmodule_layout @4Aparam_get_charp ejparam_set_charp param_get_bool >a-param_set_bool Qbpci_unregister_driver ~__pci_register_driver ;tcfb_copyarea .-cfb_fillrect κ`.memcpy cfb_imageblit "wdev_set_drvdata __request_region (pci_request_regions 5Bioremap_nocache ،/framebuffer_alloc B<pci_enable_device __const_udelay Zsnative_io_delay ?register_framebuffer Ufb_find_mode Ȑfb_alloc_cmap sstrlcpy \!pci_release_regions 4a|__release_region Yuioport_resource S9iounmap R8,framebuffer_release q fb_dealloc_cmap
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cirrusfb_open opencount cirrusfb_release cirrusfb_set_blitter bestclock __func__.24627 cirrusfb_check_pixclock cirrusfb_board_info descriptor.24075 cirrusfb_check_var descriptor.24098 cirrusfb_pci_unregister descriptor.24456 cirrusfb_pci_unmap release_io_ports cirrusfb_set_fbinfo noaccel cirrusfb_ops cirrusfb_register __func__.24441 descriptor.24442 mode_option descriptor.24445 descriptor.24449 RGen WGen WHDR vga_rseq cirrusfb_pci_register descriptor.24470 descriptor.24474 descriptor.24477 __func__.24422 descriptor.24480 cirrusfb_sync cirrusfb_WaitBLT cirrusfb_RectFill cirrusfb_imageblit cirrusfb_fillrect cirrusfb_copyarea cirrusfb_pan_display cirrusfb_check_mclk descriptor.24059 descriptor.24053 descriptor.24064 cirrusfb_set_mclk_as_source descriptor.24110 __func__.24109 cirrusfb_blank descriptor.24319 descriptor.24315 descriptor.24332 descriptor.24329 WClut cirrusfb_setcolreg init_vgachip __func__.24340 cirrusfb_set_par_foo descriptor.24280 descriptor.24177 descriptor.24180 descriptor.24153 descriptor.24156 descriptor.24159 descriptor.24162 descriptor.24150 descriptor.24283 __func__.24550 descriptor.24183 descriptor.24186 descriptor.24189 descriptor.24192 descriptor.24195 descriptor.24174 descriptor.24165 descriptor.24168 descriptor.24171 descriptor.24147 descriptor.24138 descriptor.24202 descriptor.24252 descriptor.24266 descriptor.24227 cirrusfb_set_par cirrusfb_init cirrusfb_pci_driver cirrusfb_exit __mod_noaccel2417 __mod_noacceltype2416 __param_noaccel __param_str_noaccel __mod_mode_option2415 __mod_mode_optiontype2414 __param_mode_option __param_str_mode_option __mod_license2379 __mod_description2378 __mod_author2377 cirrusfb_pci_table __func__.24457 __func__.24471 __func__.24316 __func__.24139 __func__.24054 __func__.24099 __func__.24076 __mod_srcversion74 __mod_alias72 __mod_alias71 __mod_alias70 __mod_alias69 __mod_alias68 __mod_alias67 __mod_alias66 __mod_alias65 __mod_alias64 __mod_alias63 __mod_alias62 __module_depends ____versions __mod_vermagic5 unregister_framebuffer dev_get_drvdata pci_enable_device __this_module cfb_copyarea param_get_bool native_io_delay __pci_register_driver iounmap cleanup_module pci_request_regions memcpy framebuffer_alloc param_set_charp pci_unregister_driver __release_region init_module dev_driver_string dynamic_debug_enabled fb_find_mode ioremap_nocache fb_dealloc_cmap __mod_pci_device_table strlcpy register_framebuffer param_set_bool fb_alloc_cmap printk cfb_imageblit ioport_resource param_get_charp cfb_fillrect pci_release_regions __const_udelay dynamic_debug_enabled2 dev_set_drvdata framebuffer_release __request_region ; Z + 8 U l u % D I i $ C @
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ACC SHELL 2018